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AMDGPU/GlobalISel: Legalize smulh/umulh and scalarize mul
llvm-svn: 352162
1 parent 9d70f2b commit 5d622fb

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8 files changed

+247
-3
lines changed

8 files changed

+247
-3
lines changed

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1396,6 +1396,9 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
13961396
return Legalized;
13971397
}
13981398
case TargetOpcode::G_ADD:
1399+
case TargetOpcode::G_MUL:
1400+
case TargetOpcode::G_SMULH:
1401+
case TargetOpcode::G_UMULH:
13991402
case TargetOpcode::G_FADD:
14001403
case TargetOpcode::G_FMUL:
14011404
case TargetOpcode::G_FSUB:

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
9797
setAction({G_ASHR, S32}, Legal);
9898
setAction({G_ASHR, 1, S32}, Legal);
9999
setAction({G_SUB, S32}, Legal);
100-
setAction({G_MUL, S32}, Legal);
100+
101+
getActionDefinitionsBuilder({G_MUL, G_UMULH, G_SMULH})
102+
.legalFor({S32})
103+
.scalarize(0);
101104

102105
// FIXME: 64-bit ones only legal for scalar
103106
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -586,6 +586,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
586586
case AMDGPU::G_SADDE:
587587
case AMDGPU::G_USUBE:
588588
case AMDGPU::G_SSUBE:
589+
case AMDGPU::G_UMULH:
590+
case AMDGPU::G_SMULH:
589591
if (isSALUMapping(MI))
590592
return getDefaultMappingSOP(MI);
591593
LLVM_FALLTHROUGH;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir

Lines changed: 24 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,17 +2,39 @@
22
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
33

44
---
5-
name: test_mul
5+
name: test_mul_s32
66
body: |
77
bb.0:
88
liveins: $vgpr0, $vgpr1
99
10-
; CHECK-LABEL: name: test_mul
10+
; CHECK-LABEL: name: test_mul_s32
1111
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
1212
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
1313
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
14+
; CHECK: $vgpr0 = COPY [[MUL]](s32)
1415
%0:_(s32) = COPY $vgpr0
1516
%1:_(s32) = COPY $vgpr1
1617
%2:_(s32) = G_MUL %0, %1
1718
$vgpr0 = COPY %2
1819
...
20+
21+
---
22+
name: test_mul_v2s32
23+
body: |
24+
bb.0:
25+
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
26+
27+
; CHECK-LABEL: name: test_mul_v2s32
28+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
29+
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
30+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
31+
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
32+
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]]
33+
; CHECK: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]]
34+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[MUL]](s32), [[MUL1]](s32)
35+
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
36+
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
37+
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
38+
%2:_(<2 x s32>) = G_MUL %0, %1
39+
$vgpr0_vgpr1 = COPY %2
40+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: test_smulh_s32
6+
body: |
7+
bb.0:
8+
liveins: $vgpr0, $vgpr1
9+
10+
; CHECK-LABEL: name: test_smulh_s32
11+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
12+
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
13+
; CHECK: [[SMULH:%[0-9]+]]:_(s32) = G_SMULH [[COPY]], [[COPY1]]
14+
; CHECK: $vgpr0 = COPY [[SMULH]](s32)
15+
%0:_(s32) = COPY $vgpr0
16+
%1:_(s32) = COPY $vgpr1
17+
%2:_(s32) = G_SMULH %0, %1
18+
$vgpr0 = COPY %2
19+
...
20+
21+
---
22+
name: test_smulh_v2s32
23+
body: |
24+
bb.0:
25+
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
26+
27+
; CHECK-LABEL: name: test_smulh_v2s32
28+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
29+
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
30+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
31+
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
32+
; CHECK: [[SMULH:%[0-9]+]]:_(s32) = G_SMULH [[UV]], [[UV2]]
33+
; CHECK: [[SMULH1:%[0-9]+]]:_(s32) = G_SMULH [[UV1]], [[UV3]]
34+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SMULH]](s32), [[SMULH1]](s32)
35+
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
36+
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
37+
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
38+
%2:_(<2 x s32>) = G_SMULH %0, %1
39+
$vgpr0_vgpr1 = COPY %2
40+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: test_umulh_s32
6+
body: |
7+
bb.0:
8+
liveins: $vgpr0, $vgpr1
9+
10+
; CHECK-LABEL: name: test_umulh_s32
11+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
12+
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
13+
; CHECK: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
14+
; CHECK: $vgpr0 = COPY [[UMULH]](s32)
15+
%0:_(s32) = COPY $vgpr0
16+
%1:_(s32) = COPY $vgpr1
17+
%2:_(s32) = G_UMULH %0, %1
18+
$vgpr0 = COPY %2
19+
...
20+
21+
---
22+
name: test_umulh_v2s32
23+
body: |
24+
bb.0:
25+
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
26+
27+
; CHECK-LABEL: name: test_umulh_v2s32
28+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
29+
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
30+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
31+
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
32+
; CHECK: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[UV]], [[UV2]]
33+
; CHECK: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[UV1]], [[UV3]]
34+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMULH]](s32), [[UMULH1]](s32)
35+
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
36+
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
37+
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
38+
%2:_(<2 x s32>) = G_UMULH %0, %1
39+
$vgpr0_vgpr1 = COPY %2
40+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3+
4+
---
5+
name: smulh_s32_ss
6+
legalized: true
7+
8+
body: |
9+
bb.0:
10+
liveins: $sgpr0, $sgpr1
11+
; CHECK-LABEL: name: smulh_s32_ss
12+
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
13+
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
14+
; CHECK: [[SMULH:%[0-9]+]]:sgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
15+
%0:_(s32) = COPY $sgpr0
16+
%1:_(s32) = COPY $sgpr1
17+
%2:_(s32) = G_SMULH %0, %1
18+
...
19+
20+
---
21+
name: smulh_s32_sv
22+
legalized: true
23+
24+
body: |
25+
bb.0:
26+
liveins: $sgpr0, $vgpr0
27+
; CHECK-LABEL: name: smulh_s32_sv
28+
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
29+
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
30+
; CHECK: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
31+
%0:_(s32) = COPY $sgpr0
32+
%1:_(s32) = COPY $vgpr0
33+
%2:_(s32) = G_SMULH %0, %1
34+
...
35+
36+
---
37+
name: smulh_s32_vs
38+
legalized: true
39+
40+
body: |
41+
bb.0:
42+
liveins: $sgpr0, $vgpr0
43+
; CHECK-LABEL: name: smulh_s32_vs
44+
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
45+
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
46+
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
47+
; CHECK: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY2]]
48+
%0:_(s32) = COPY $vgpr0
49+
%1:_(s32) = COPY $sgpr0
50+
%2:_(s32) = G_SMULH %0, %1
51+
...
52+
53+
---
54+
name: smulh_s32_vv
55+
legalized: true
56+
57+
body: |
58+
bb.0:
59+
liveins: $vgpr0, $vgpr1
60+
; CHECK-LABEL: name: smulh_s32_vv
61+
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
62+
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
63+
; CHECK: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
64+
%0:_(s32) = COPY $vgpr0
65+
%1:_(s32) = COPY $vgpr1
66+
%2:_(s32) = G_SMULH %0, %1
67+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3+
4+
---
5+
name: umulh_s32_ss
6+
legalized: true
7+
8+
body: |
9+
bb.0:
10+
liveins: $sgpr0, $sgpr1
11+
; CHECK-LABEL: name: umulh_s32_ss
12+
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
13+
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
14+
; CHECK: [[UMULH:%[0-9]+]]:sgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
15+
%0:_(s32) = COPY $sgpr0
16+
%1:_(s32) = COPY $sgpr1
17+
%2:_(s32) = G_UMULH %0, %1
18+
...
19+
20+
---
21+
name: umulh_s32_sv
22+
legalized: true
23+
24+
body: |
25+
bb.0:
26+
liveins: $sgpr0, $vgpr0
27+
; CHECK-LABEL: name: umulh_s32_sv
28+
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
29+
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
30+
; CHECK: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
31+
%0:_(s32) = COPY $sgpr0
32+
%1:_(s32) = COPY $vgpr0
33+
%2:_(s32) = G_UMULH %0, %1
34+
...
35+
36+
---
37+
name: umulh_s32_vs
38+
legalized: true
39+
40+
body: |
41+
bb.0:
42+
liveins: $sgpr0, $vgpr0
43+
; CHECK-LABEL: name: umulh_s32_vs
44+
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
45+
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
46+
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
47+
; CHECK: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY2]]
48+
%0:_(s32) = COPY $vgpr0
49+
%1:_(s32) = COPY $sgpr0
50+
%2:_(s32) = G_UMULH %0, %1
51+
...
52+
53+
---
54+
name: umulh_s32_vv
55+
legalized: true
56+
57+
body: |
58+
bb.0:
59+
liveins: $vgpr0, $vgpr1
60+
; CHECK-LABEL: name: umulh_s32_vv
61+
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
62+
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
63+
; CHECK: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
64+
%0:_(s32) = COPY $vgpr0
65+
%1:_(s32) = COPY $vgpr1
66+
%2:_(s32) = G_UMULH %0, %1
67+
...

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