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[SelectionDAG][Targets] Replace atomic_load_8/atomic_load_16 with atomic_load_*ext_8/atomic_load_*ext_16 where possible. (#137279)
isAnyExtLoad/isZExtLoad/isSignExtLoad are able to emit predicate checks from tablegen now so we should use them. The next step would be to add isNonExtLoad versions and migrate all remaining uses of atomic_load_8/16/32/64 to that.
1 parent 3ce2d1e commit 5dc2d66

22 files changed

+116
-92
lines changed

‎llvm/include/llvm/Target/TargetSelectionDAG.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1947,6 +1947,11 @@ def atomic_load_azext_16 : PatFrags<(ops node:$op),
19471947
[(atomic_load_aext_16 node:$op),
19481948
(atomic_load_zext_16 node:$op)]>;
19491949

1950+
// Atomic load which zeroes or anyextends the high bits.
1951+
def atomic_load_azext_32 : PatFrags<(ops node:$op),
1952+
[(atomic_load_aext_32 node:$op),
1953+
(atomic_load_zext_32 node:$op)]>;
1954+
19501955
// Atomic load which sign extends or anyextends the high bits.
19511956
def atomic_load_asext_8 : PatFrags<(ops node:$op),
19521957
[(atomic_load_aext_8 node:$op),

‎llvm/lib/Target/AArch64/AArch64InstrAtomics.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,9 +51,9 @@ class seq_cst_load<PatFrags base>
5151
let Predicates = [HasRCPC] in {
5252
// v8.3 Release Consistent Processor Consistent support, optional in v8.2.
5353
// 8-bit loads
54-
def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDAPRB GPR64sp:$ptr)>;
54+
def : Pat<(acquiring_load<atomic_load_azext_8> GPR64sp:$ptr), (LDAPRB GPR64sp:$ptr)>;
5555
// 16-bit loads
56-
def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDAPRH GPR64sp:$ptr)>;
56+
def : Pat<(acquiring_load<atomic_load_azext_16> GPR64sp:$ptr), (LDAPRH GPR64sp:$ptr)>;
5757
// 32-bit loads
5858
def : Pat<(acquiring_load<atomic_load_32> GPR64sp:$ptr), (LDAPRW GPR64sp:$ptr)>;
5959
// 64-bit loads

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -502,10 +502,6 @@ def zextloadi16_#as : PatFrag<(ops node:$ptr), (zextloadi16 node:$ptr)> {
502502
let IsLoad = 1;
503503
}
504504

505-
def atomic_load_8_#as : PatFrag<(ops node:$ptr), (atomic_load_8 node:$ptr)> {
506-
let IsAtomic = 1;
507-
}
508-
509505
def atomic_load_16_#as : PatFrag<(ops node:$ptr), (atomic_load_16 node:$ptr)> {
510506
let IsAtomic = 1;
511507
}
@@ -526,6 +522,10 @@ def atomic_load_sext_8_#as : PatFrag<(ops node:$ptr), (atomic_load_sext_8 node:$
526522
let IsAtomic = 1;
527523
}
528524

525+
def atomic_load_aext_8_#as : PatFrag<(ops node:$ptr), (atomic_load_aext_8 node:$ptr)> {
526+
let IsAtomic = 1;
527+
}
528+
529529
def atomic_load_zext_16_#as : PatFrag<(ops node:$ptr), (atomic_load_zext_16 node:$ptr)> {
530530
let IsAtomic = 1;
531531
}
@@ -534,6 +534,10 @@ def atomic_load_sext_16_#as : PatFrag<(ops node:$ptr), (atomic_load_sext_16 node
534534
let IsAtomic = 1;
535535
}
536536

537+
def atomic_load_aext_16_#as : PatFrag<(ops node:$ptr), (atomic_load_aext_16 node:$ptr)> {
538+
let IsAtomic = 1;
539+
}
540+
537541
} // End let AddressSpaces
538542
} // End foreach as
539543

‎llvm/lib/Target/AMDGPU/BUFInstructions.td

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -953,11 +953,12 @@ defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads_Lds <
953953
"buffer_load_dwordx4", v4i32, /*LDSPred=*/HasGFX950Insts
954954
>;
955955

956-
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_8_global>;
956+
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_aext_8_global>;
957957
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_zext_8_global>;
958-
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_16_global>;
958+
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_aext_16_global>;
959959
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_zext_16_global>;
960-
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_8_global>;
960+
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_aext_8_global>;
961+
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_zext_8_global>;
961962
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i16, atomic_load_16_global>;
962963
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, extloadi8_global>;
963964
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, zextloadi8_global>;

‎llvm/lib/Target/AMDGPU/DSInstructions.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -853,14 +853,14 @@ foreach vt = Reg32Types.types in {
853853
defm : DSReadPat_mc <DS_READ_B32, vt, "load_local">;
854854
}
855855

856-
defm : DSReadPat_t16 <DS_READ_U8, i16, "atomic_load_8_local">;
857-
defm : DSReadPat_mc <DS_READ_U8, i32, "atomic_load_8_local">;
856+
defm : DSReadPat_t16 <DS_READ_U8, i16, "atomic_load_aext_8_local">;
857+
defm : DSReadPat_mc <DS_READ_U8, i32, "atomic_load_aext_8_local">;
858858
defm : DSReadPat_t16 <DS_READ_U8, i16, "atomic_load_zext_8_local">;
859859
defm : DSReadPat_mc <DS_READ_U8, i32, "atomic_load_zext_8_local">;
860860
defm : DSReadPat_t16 <DS_READ_I8, i16, "atomic_load_sext_8_local">;
861861
defm : DSReadPat_mc <DS_READ_I8, i32, "atomic_load_sext_8_local">;
862862
defm : DSReadPat_t16 <DS_READ_U16, i16, "atomic_load_16_local">;
863-
defm : DSReadPat_mc <DS_READ_U16, i32, "atomic_load_16_local">;
863+
defm : DSReadPat_mc <DS_READ_U16, i32, "atomic_load_aext_16_local">;
864864
defm : DSReadPat_mc <DS_READ_U16, i32, "atomic_load_zext_16_local">;
865865
defm : DSReadPat_mc <DS_READ_I16, i32, "atomic_load_sext_16_local">;
866866
defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;

‎llvm/lib/Target/AMDGPU/FLATInstructions.td

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1536,14 +1536,13 @@ multiclass ScratchFLATLoadPats_D16_t16<string inst, SDPatternOperator node, Valu
15361536

15371537
let OtherPredicates = [HasFlatAddressSpace] in {
15381538

1539-
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_8_flat, i32>;
1540-
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_8_flat, i16>;
1539+
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_aext_8_flat, i32>;
1540+
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_aext_8_flat, i16>;
15411541
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_zext_8_flat, i32>;
15421542
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_zext_8_flat, i16>;
1543-
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_16_flat, i32>;
1543+
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_aext_16_flat, i32>;
15441544
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_16_flat, i16>;
15451545
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_zext_16_flat, i32>;
1546-
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_zext_16_flat, i16>;
15471546
def : FlatLoadPat <FLAT_LOAD_UBYTE, extloadi8_flat, i32>;
15481547
def : FlatLoadPat <FLAT_LOAD_UBYTE, zextloadi8_flat, i32>;
15491548
def : FlatLoadPat <FLAT_LOAD_SBYTE, sextloadi8_flat, i32>;
@@ -1678,11 +1677,11 @@ def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16, load_d16_lo_flat, v2f16>;
16781677

16791678
let OtherPredicates = [HasFlatGlobalInsts] in {
16801679

1681-
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_8_global, i32>;
1682-
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_8_global, i16>;
1680+
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_aext_8_global, i32>;
1681+
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_aext_8_global, i16>;
16831682
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_zext_8_global, i32>;
16841683
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_zext_8_global, i16>;
1685-
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_16_global, i32>;
1684+
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_aext_16_global, i32>;
16861685
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_16_global, i16>;
16871686
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_zext_16_global, i32>;
16881687
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_zext_16_global, i16>;

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 20 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -373,10 +373,10 @@ def atomic_load_sext_glue :
373373
let IsSignExtLoad = true;
374374
}
375375

376-
def atomic_load_8_glue : PatFrag<(ops node:$ptr),
377-
(AMDGPUatomic_ld_glue node:$ptr)> {
378-
let IsAtomic = 1;
379-
let MemoryVT = i8;
376+
def atomic_load_aext_glue :
377+
PatFrag<(ops node:$ptr), (AMDGPUatomic_ld_glue node:$ptr)> {
378+
let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
379+
let IsAnyExtLoad = true;
380380
}
381381

382382
def atomic_load_16_glue : PatFrag<(ops node:$ptr),
@@ -409,6 +409,12 @@ def atomic_load_sext_8_glue : PatFrag<(ops node:$ptr),
409409
let MemoryVT = i8;
410410
}
411411

412+
def atomic_load_aext_8_glue : PatFrag<(ops node:$ptr),
413+
(atomic_load_aext_glue node:$ptr)> {
414+
let IsAtomic = 1;
415+
let MemoryVT = i8;
416+
}
417+
412418
def atomic_load_zext_16_glue : PatFrag<(ops node:$ptr),
413419
(atomic_load_zext_glue node:$ptr)> {
414420
let IsAtomic = 1;
@@ -421,6 +427,12 @@ def atomic_load_sext_16_glue : PatFrag<(ops node:$ptr),
421427
let MemoryVT = i16;
422428
}
423429

430+
def atomic_load_aext_16_glue : PatFrag<(ops node:$ptr),
431+
(atomic_load_aext_glue node:$ptr)> {
432+
let IsAtomic = 1;
433+
let MemoryVT = i16;
434+
}
435+
424436
def extload_glue : PatFrag<(ops node:$ptr), (unindexedload_glue node:$ptr)> {
425437
let IsLoad = 1;
426438
let IsAnyExtLoad = 1;
@@ -494,8 +506,6 @@ def load_align16_local_m0 : PatFrag<(ops node:$ptr),
494506
}
495507

496508
let IsAtomic = 1, AddressSpaces = LoadAddress_local.AddrSpaces in {
497-
def atomic_load_8_local_m0 : PatFrag<(ops node:$ptr),
498-
(atomic_load_8_glue node:$ptr)>;
499509
def atomic_load_16_local_m0 : PatFrag<(ops node:$ptr),
500510
(atomic_load_16_glue node:$ptr)>;
501511
def atomic_load_32_local_m0 : PatFrag<(ops node:$ptr),
@@ -507,10 +517,14 @@ def atomic_load_zext_8_local_m0 : PatFrag<(ops node:$ptr),
507517
(atomic_load_zext_8_glue node:$ptr)>;
508518
def atomic_load_sext_8_local_m0 : PatFrag<(ops node:$ptr),
509519
(atomic_load_sext_8_glue node:$ptr)>;
520+
def atomic_load_aext_8_local_m0 : PatFrag<(ops node:$ptr),
521+
(atomic_load_aext_8_glue node:$ptr)>;
510522
def atomic_load_zext_16_local_m0 : PatFrag<(ops node:$ptr),
511523
(atomic_load_zext_16_glue node:$ptr)>;
512524
def atomic_load_sext_16_local_m0 : PatFrag<(ops node:$ptr),
513525
(atomic_load_sext_16_glue node:$ptr)>;
526+
def atomic_load_aext_16_local_m0 : PatFrag<(ops node:$ptr),
527+
(atomic_load_aext_16_glue node:$ptr)>;
514528
} // End let AddressSpaces = LoadAddress_local.AddrSpaces
515529

516530

‎llvm/lib/Target/ARM/ARMInstrInfo.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5376,14 +5376,14 @@ def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
53765376
def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
53775377
(STLEXH GPR:$Rt, addr_offset_none:$addr)>;
53785378

5379-
class acquiring_load<PatFrag base>
5379+
class acquiring_load<PatFrags base>
53805380
: PatFrag<(ops node:$ptr), (base node:$ptr), [{
53815381
AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getSuccessOrdering();
53825382
return isAcquireOrStronger(Ordering);
53835383
}]>;
53845384

5385-
def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
5386-
def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
5385+
def atomic_load_azext_acquire_8 : acquiring_load<atomic_load_azext_8>;
5386+
def atomic_load_azext_acquire_16 : acquiring_load<atomic_load_azext_16>;
53875387
def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
53885388

53895389
class releasing_store<PatFrag base>
@@ -5397,8 +5397,8 @@ def atomic_store_release_16 : releasing_store<atomic_store_16>;
53975397
def atomic_store_release_32 : releasing_store<atomic_store_32>;
53985398

53995399
let AddedComplexity = 8 in {
5400-
def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
5401-
def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
5400+
def : ARMPat<(atomic_load_azext_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
5401+
def : ARMPat<(atomic_load_azext_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
54025402
def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
54035403
def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
54045404
def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
@@ -6214,11 +6214,11 @@ def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
62146214
(SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
62156215

62166216
// Atomic load/store patterns
6217-
def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
6217+
def : ARMPat<(atomic_load_azext_8 ldst_so_reg:$src),
62186218
(LDRBrs ldst_so_reg:$src)>;
6219-
def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
6219+
def : ARMPat<(atomic_load_azext_8 addrmode_imm12:$src),
62206220
(LDRBi12 addrmode_imm12:$src)>;
6221-
def : ARMPat<(atomic_load_16 addrmode3:$src),
6221+
def : ARMPat<(atomic_load_azext_16 addrmode3:$src),
62226222
(LDRH addrmode3:$src)>;
62236223
def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
62246224
(LDRrs ldst_so_reg:$src)>;

‎llvm/lib/Target/ARM/ARMInstrThumb.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1697,13 +1697,13 @@ def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
16971697
def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
16981698
(tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>;
16991699

1700-
def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1700+
def : T1Pat<(atomic_load_azext_8 t_addrmode_is1:$src),
17011701
(tLDRBi t_addrmode_is1:$src)>;
1702-
def : T1Pat<(atomic_load_8 t_addrmode_rr:$src),
1702+
def : T1Pat<(atomic_load_azext_8 t_addrmode_rr:$src),
17031703
(tLDRBr t_addrmode_rr:$src)>;
1704-
def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1704+
def : T1Pat<(atomic_load_azext_16 t_addrmode_is2:$src),
17051705
(tLDRHi t_addrmode_is2:$src)>;
1706-
def : T1Pat<(atomic_load_16 t_addrmode_rr:$src),
1706+
def : T1Pat<(atomic_load_azext_16 t_addrmode_rr:$src),
17071707
(tLDRHr t_addrmode_rr:$src)>;
17081708
def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
17091709
(tLDRi t_addrmode_is4:$src)>;

‎llvm/lib/Target/ARM/ARMInstrThumb2.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4899,17 +4899,17 @@ def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
48994899
Requires<[HasDSP, IsThumb2]>;
49004900

49014901
// Atomic load/store patterns
4902-
def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
4902+
def : T2Pat<(atomic_load_azext_8 t2addrmode_imm12:$addr),
49034903
(t2LDRBi12 t2addrmode_imm12:$addr)>;
4904-
def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
4904+
def : T2Pat<(atomic_load_azext_8 t2addrmode_negimm8:$addr),
49054905
(t2LDRBi8 t2addrmode_negimm8:$addr)>;
4906-
def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
4906+
def : T2Pat<(atomic_load_azext_8 t2addrmode_so_reg:$addr),
49074907
(t2LDRBs t2addrmode_so_reg:$addr)>;
4908-
def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
4908+
def : T2Pat<(atomic_load_azext_16 t2addrmode_imm12:$addr),
49094909
(t2LDRHi12 t2addrmode_imm12:$addr)>;
4910-
def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
4910+
def : T2Pat<(atomic_load_azext_16 t2addrmode_negimm8:$addr),
49114911
(t2LDRHi8 t2addrmode_negimm8:$addr)>;
4912-
def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
4912+
def : T2Pat<(atomic_load_azext_16 t2addrmode_so_reg:$addr),
49134913
(t2LDRHs t2addrmode_so_reg:$addr)>;
49144914
def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
49154915
(t2LDRi12 t2addrmode_imm12:$addr)>;
@@ -4937,8 +4937,8 @@ def : T2Pat<(atomic_store_32 GPR:$val, t2addrmode_so_reg:$addr),
49374937
(t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
49384938

49394939
let AddedComplexity = 8, Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex] in {
4940-
def : Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;
4941-
def : Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;
4940+
def : Pat<(atomic_load_azext_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;
4941+
def : Pat<(atomic_load_azext_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;
49424942
def : Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>;
49434943
def : Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>;
49444944
def : Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>;

‎llvm/lib/Target/Hexagon/HexagonPatterns.td

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2130,7 +2130,7 @@ def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
21302130

21312131
// Patterns to select load-indexed: Rs + Off.
21322132
// - frameindex [+ imm],
2133-
multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
2133+
multiclass Loadxfi_pat<PatFrags Load, ValueType VT, PatLeaf ImmPred,
21342134
InstHexagon MI> {
21352135
def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
21362136
(VT (MI AddrFI:$fi, imm:$Off))>;
@@ -2141,7 +2141,7 @@ multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
21412141

21422142
// Patterns to select load-indexed: Rs + Off.
21432143
// - base reg [+ imm]
2144-
multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
2144+
multiclass Loadxgi_pat<PatFrags Load, ValueType VT, PatLeaf ImmPred,
21452145
InstHexagon MI> {
21462146
def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))),
21472147
(VT (MI IntRegs:$Rs, imm:$Off))>;
@@ -2151,7 +2151,7 @@ multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
21512151
}
21522152

21532153
// Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi.
2154-
multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
2154+
multiclass Loadxi_pat<PatFrags Load, ValueType VT, PatLeaf ImmPred,
21552155
InstHexagon MI> {
21562156
defm: Loadxfi_pat<Load, VT, ImmPred, MI>;
21572157
defm: Loadxgi_pat<Load, VT, ImmPred, MI>;
@@ -2221,7 +2221,7 @@ class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod,
22212221
(VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>;
22222222

22232223
// Pattern to select load absolute.
2224-
class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
2224+
class Loada_pat<PatFrags Load, ValueType VT, PatFrag Addr, InstHexagon MI>
22252225
: Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;
22262226

22272227
// Pattern to select load absolute with value modifier.
@@ -2256,8 +2256,8 @@ let AddedComplexity = 20 in {
22562256
defm: Loadxi_pat<load, f64, anyimm3, L2_loadrd_io>;
22572257
// No sextloadi1.
22582258

2259-
defm: Loadxi_pat<atomic_load_8 , i32, anyimm0, L2_loadrub_io>;
2260-
defm: Loadxi_pat<atomic_load_16, i32, anyimm1, L2_loadruh_io>;
2259+
defm: Loadxi_pat<atomic_load_azext_8 , i32, anyimm0, L2_loadrub_io>;
2260+
defm: Loadxi_pat<atomic_load_azext_16, i32, anyimm1, L2_loadruh_io>;
22612261
defm: Loadxi_pat<atomic_load_32, i32, anyimm2, L2_loadri_io>;
22622262
defm: Loadxi_pat<atomic_load_64, i64, anyimm3, L2_loadrd_io>;
22632263
}
@@ -2418,8 +2418,8 @@ let AddedComplexity = 60 in {
24182418
def: Loada_pat<load, f32, anyimm2, PS_loadriabs>;
24192419
def: Loada_pat<load, f64, anyimm3, PS_loadrdabs>;
24202420

2421-
def: Loada_pat<atomic_load_8, i32, anyimm0, PS_loadrubabs>;
2422-
def: Loada_pat<atomic_load_16, i32, anyimm1, PS_loadruhabs>;
2421+
def: Loada_pat<atomic_load_azext_8, i32, anyimm0, PS_loadrubabs>;
2422+
def: Loada_pat<atomic_load_azext_16, i32, anyimm1, PS_loadruhabs>;
24232423
def: Loada_pat<atomic_load_32, i32, anyimm2, PS_loadriabs>;
24242424
def: Loada_pat<atomic_load_64, i64, anyimm3, PS_loadrdabs>;
24252425
}
@@ -2463,8 +2463,8 @@ let AddedComplexity = 100 in {
24632463
def: Loada_pat<load, f32, addrgp, L2_loadrigp>;
24642464
def: Loada_pat<load, f64, addrgp, L2_loadrdgp>;
24652465

2466-
def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>;
2467-
def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
2466+
def: Loada_pat<atomic_load_azext_8, i32, addrgp, L2_loadrubgp>;
2467+
def: Loada_pat<atomic_load_azext_16, i32, addrgp, L2_loadruhgp>;
24682468
def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
24692469
def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
24702470
}

‎llvm/lib/Target/Lanai/LanaiInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -845,7 +845,7 @@ def : Pat<(extloadi16 ADDRspls:$src), (i32 (LDHz_RI ADDRspls:$src))>;
845845
// Loads up to 32-bits are already atomic.
846846
// TODO: This is a workaround for a particular failing case and should be
847847
// handled more generally.
848-
def : Pat<(atomic_load_8 ADDRspls:$src), (i32 (LDBz_RI ADDRspls:$src))>;
848+
def : Pat<(atomic_load_azext_8 ADDRspls:$src), (i32 (LDBz_RI ADDRspls:$src))>;
849849

850850
// GlobalAddress, ExternalSymbol, Jumptable, ConstantPool
851851
def : Pat<(LanaiHi tglobaladdr:$dst), (MOVHI tglobaladdr:$dst)>;

‎llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1779,7 +1779,7 @@ def : Pat<(bitreverse (bswap GPR:$rj)), (BITREV_8B GPR:$rj)>;
17791779

17801780
/// Loads
17811781

1782-
multiclass LdPat<PatFrag LoadOp, LAInst Inst, ValueType vt = GRLenVT> {
1782+
multiclass LdPat<PatFrags LoadOp, LAInst Inst, ValueType vt = GRLenVT> {
17831783
def : Pat<(vt (LoadOp BaseAddr:$rj)), (Inst BaseAddr:$rj, 0)>;
17841784
def : Pat<(vt (LoadOp (AddrConstant GPR:$rj, simm12:$imm12))),
17851785
(Inst GPR:$rj, simm12:$imm12)>;
@@ -1890,9 +1890,10 @@ def : Pat<(atomic_fence 5, timm), (DBAR 0b10010)>; // release
18901890
def : Pat<(atomic_fence 6, timm), (DBAR 0b10000)>; // acqrel
18911891
def : Pat<(atomic_fence 7, timm), (DBAR 0b10000)>; // seqcst
18921892

1893-
defm : LdPat<atomic_load_8, LD_B>;
1894-
defm : LdPat<atomic_load_16, LD_H>;
1895-
defm : LdPat<atomic_load_32, LD_W>;
1893+
defm : LdPat<atomic_load_asext_8, LD_B>;
1894+
defm : LdPat<atomic_load_asext_16, LD_H>;
1895+
defm : LdPat<atomic_load_32, LD_W>, Requires<[IsLA32]>;
1896+
defm : LdPat<atomic_load_asext_32, LD_W>, Requires<[IsLA64]>;
18961897

18971898
class release_seqcst_store<PatFrag base>
18981899
: PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr), [{

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