@@ -714,6 +714,8 @@ static unsigned int getCodeAddrSpace(MemSDNode *N) {
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return NVPTX::PTXLdStInstCode::GENERIC;
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}
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+ namespace {
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+
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struct OperationOrderings {
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NVPTX::OrderingUnderlyingType InstrOrdering;
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NVPTX::OrderingUnderlyingType FenceOrdering;
@@ -907,11 +909,11 @@ getOperationOrderings(MemSDNode *N, const NVPTXSubtarget *Subtarget) {
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// This sets the ordering of the fence to SequentiallyConsistent, and
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// sets the corresponding ordering for the instruction.
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NVPTX::Ordering InstrOrder;
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- if (N->readMem ()) {
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+ if (N->readMem ())
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InstrOrder = NVPTX::Ordering::Acquire;
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- } else if (N->writeMem ()) {
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+ else if (N->writeMem ())
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InstrOrder = NVPTX::Ordering::Release;
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- } else {
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+ else {
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SmallString<256 > Msg;
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raw_svector_ostream OS (Msg);
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OS << " NVPTX does not support SequentiallyConsistent Ordering on "
@@ -934,6 +936,8 @@ getOperationOrderings(MemSDNode *N, const NVPTXSubtarget *Subtarget) {
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report_fatal_error (OS.str ());
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}
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+ } // namespace
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+
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static bool canLowerToLDG (MemSDNode *N, const NVPTXSubtarget &Subtarget,
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unsigned CodeAddrSpace, MachineFunction *F) {
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// We use ldg (i.e. ld.global.nc) for invariant loads from the global address
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