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[GlobalISel] Add a getTargetLowering method to IRTranslator. NFC
This adds a common convenience function for getting the TargetLowering. The alternative would be to store TLI as a variable too.
1 parent e510fc7 commit 5e0d62b

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2 files changed

+21
-17
lines changed

2 files changed

+21
-17
lines changed

llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -624,6 +624,10 @@ class IRTranslator : public MachineFunctionPass {
624624

625625
StackProtectorDescriptor SPDescriptor;
626626

627+
const TargetLowering &getTargetLowering() {
628+
return *MF->getSubtarget().getTargetLowering();
629+
}
630+
627631
/// Switch analysis and optimization.
628632
class GISelSwitchLowering : public SwitchCG::SwitchLowering {
629633
public:

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -596,7 +596,7 @@ bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
596596
const Value *CondVal = BrInst.getCondition();
597597
MachineBasicBlock *Succ1MBB = &getMBB(*BrInst.getSuccessor(1));
598598

599-
const auto &TLI = *MF->getSubtarget().getTargetLowering();
599+
const auto &TLI = getTargetLowering();
600600

601601
// If this is a series of conditions that are or'd or and'd together, emit
602602
// this as a sequence of branches instead of setcc's with and/or operations.
@@ -1385,7 +1385,7 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
13851385
return true;
13861386
}
13871387

1388-
auto &TLI = *MF->getSubtarget().getTargetLowering();
1388+
auto &TLI = getTargetLowering();
13891389
MachineMemOperand::Flags Flags =
13901390
TLI.getLoadMemOperandFlags(LI, *DL, AC, LibInfo);
13911391
if (AA && !(Flags & MachineMemOperand::MOInvariant)) {
@@ -1434,7 +1434,7 @@ bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
14341434
return true;
14351435
}
14361436

1437-
auto &TLI = *MF->getSubtarget().getTargetLowering();
1437+
auto &TLI = getTargetLowering();
14381438
MachineMemOperand::Flags Flags = TLI.getStoreMemOperandFlags(SI, *DL);
14391439

14401440
for (unsigned i = 0; i < Vals.size(); ++i) {
@@ -1779,7 +1779,7 @@ void IRTranslator::getStackGuard(Register DstReg,
17791779
auto MIB =
17801780
MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {});
17811781

1782-
auto &TLI = *MF->getSubtarget().getTargetLowering();
1782+
auto &TLI = getTargetLowering();
17831783
Value *Global = TLI.getSDagStackGuard(*MF->getFunction().getParent());
17841784
if (!Global)
17851785
return;
@@ -2111,7 +2111,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
21112111
// does. Simplest intrinsic ever!
21122112
return true;
21132113
case Intrinsic::vastart: {
2114-
auto &TLI = *MF->getSubtarget().getTargetLowering();
2114+
auto &TLI = getTargetLowering();
21152115
Value *Ptr = CI.getArgOperand(0);
21162116
unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
21172117
Align Alignment = getKnownAlignment(Ptr, *DL);
@@ -2189,7 +2189,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
21892189
return translateFixedPointIntrinsic(TargetOpcode::G_UDIVFIXSAT, CI, MIRBuilder);
21902190
case Intrinsic::fmuladd: {
21912191
const TargetMachine &TM = MF->getTarget();
2192-
const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
2192+
const TargetLowering &TLI = getTargetLowering();
21932193
Register Dst = getOrCreateVReg(CI);
21942194
Register Op0 = getOrCreateVReg(*CI.getArgOperand(0));
21952195
Register Op1 = getOrCreateVReg(*CI.getArgOperand(1));
@@ -2254,7 +2254,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
22542254
getStackGuard(getOrCreateVReg(CI), MIRBuilder);
22552255
return true;
22562256
case Intrinsic::stackprotector: {
2257-
const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
2257+
const TargetLowering &TLI = getTargetLowering();
22582258
LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
22592259
Register GuardVal;
22602260
if (TLI.useLoadStackGuardNode()) {
@@ -2635,7 +2635,7 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
26352635
}
26362636

26372637
// Add a MachineMemOperand if it is a target mem intrinsic.
2638-
const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
2638+
const TargetLowering &TLI = getTargetLowering();
26392639
TargetLowering::IntrinsicInfo Info;
26402640
// TODO: Add a GlobalISel version of getTgtMemIntrinsic.
26412641
if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) {
@@ -2818,7 +2818,7 @@ bool IRTranslator::translateLandingPad(const User &U,
28182818

28192819
// If there aren't registers to copy the values into (e.g., during SjLj
28202820
// exceptions), then don't bother.
2821-
auto &TLI = *MF->getSubtarget().getTargetLowering();
2821+
auto &TLI = getTargetLowering();
28222822
const Constant *PersonalityFn = MF->getFunction().getPersonalityFn();
28232823
if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
28242824
TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
@@ -2986,7 +2986,7 @@ bool IRTranslator::translateExtractElement(const User &U,
29862986

29872987
Register Res = getOrCreateVReg(U);
29882988
Register Val = getOrCreateVReg(*U.getOperand(0));
2989-
const auto &TLI = *MF->getSubtarget().getTargetLowering();
2989+
const auto &TLI = getTargetLowering();
29902990
unsigned PreferredVecIdxWidth = TLI.getVectorIdxTy(*DL).getSizeInBits();
29912991
Register Idx;
29922992
if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(1))) {
@@ -3039,7 +3039,7 @@ bool IRTranslator::translateAtomicCmpXchg(const User &U,
30393039
MachineIRBuilder &MIRBuilder) {
30403040
const AtomicCmpXchgInst &I = cast<AtomicCmpXchgInst>(U);
30413041

3042-
auto &TLI = *MF->getSubtarget().getTargetLowering();
3042+
auto &TLI = getTargetLowering();
30433043
auto Flags = TLI.getAtomicMemOperandFlags(I, *DL);
30443044

30453045
auto Res = getOrCreateVRegs(I);
@@ -3061,7 +3061,7 @@ bool IRTranslator::translateAtomicCmpXchg(const User &U,
30613061
bool IRTranslator::translateAtomicRMW(const User &U,
30623062
MachineIRBuilder &MIRBuilder) {
30633063
const AtomicRMWInst &I = cast<AtomicRMWInst>(U);
3064-
auto &TLI = *MF->getSubtarget().getTargetLowering();
3064+
auto &TLI = getTargetLowering();
30653065
auto Flags = TLI.getAtomicMemOperandFlags(I, *DL);
30663066

30673067
Register Res = getOrCreateVReg(I);
@@ -3302,7 +3302,7 @@ bool IRTranslator::translate(const Instruction &Inst) {
33023302
CurBuilder->setDebugLoc(Inst.getDebugLoc());
33033303
CurBuilder->setPCSections(Inst.getMetadata(LLVMContext::MD_pcsections));
33043304

3305-
auto &TLI = *MF->getSubtarget().getTargetLowering();
3305+
auto &TLI = getTargetLowering();
33063306
if (TLI.fallBackToDAGISel(Inst))
33073307
return false;
33083308

@@ -3454,7 +3454,7 @@ bool IRTranslator::finalizeBasicBlock(const BasicBlock &BB,
34543454
// Check if we need to generate stack-protector guard checks.
34553455
StackProtector &SP = getAnalysis<StackProtector>();
34563456
if (SP.shouldEmitSDCheck(BB)) {
3457-
const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
3457+
const TargetLowering &TLI = getTargetLowering();
34583458
bool FunctionBasedInstrumentation =
34593459
TLI.getSSPStackGuardCheck(*MF->getFunction().getParent());
34603460
SPDescriptor.initialize(&BB, &MBB, FunctionBasedInstrumentation);
@@ -3501,7 +3501,7 @@ bool IRTranslator::emitSPDescriptorParent(StackProtectorDescriptor &SPD,
35013501
MachineBasicBlock *ParentBB) {
35023502
CurBuilder->setInsertPt(*ParentBB, ParentBB->end());
35033503
// First create the loads to the guard/stack slot for the comparison.
3504-
const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
3504+
const TargetLowering &TLI = getTargetLowering();
35053505
Type *PtrIRTy = PointerType::getUnqual(MF->getFunction().getContext());
35063506
const LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
35073507
LLT PtrMemTy = getLLTForMVT(TLI.getPointerMemTy(*DL));
@@ -3593,7 +3593,7 @@ bool IRTranslator::emitSPDescriptorParent(StackProtectorDescriptor &SPD,
35933593
bool IRTranslator::emitSPDescriptorFailure(StackProtectorDescriptor &SPD,
35943594
MachineBasicBlock *FailureBB) {
35953595
CurBuilder->setInsertPt(*FailureBB, FailureBB->end());
3596-
const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
3596+
const TargetLowering &TLI = getTargetLowering();
35973597

35983598
const RTLIB::Libcall Libcall = RTLIB::STACKPROTECTOR_CHECK_FAIL;
35993599
const char *Name = TLI.getLibcallName(Libcall);
@@ -3696,7 +3696,7 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
36963696
LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
36973697
FuncInfo.CanLowerReturn = CLI->checkReturnTypeForCallConv(*MF);
36983698

3699-
const auto &TLI = *MF->getSubtarget().getTargetLowering();
3699+
const auto &TLI = getTargetLowering();
37003700

37013701
SL = std::make_unique<GISelSwitchLowering>(this, FuncInfo);
37023702
SL->init(TLI, TM, *DL);

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