[WIP][AArch64] Support CodeView debug info with SVE.

From quick testing, there are two major things that need to be added to
make the debug info work: one, we need to encode the register numbers
themselves into the debug info, and two, we need to be able to encode
the offsets of SVE variables on the stack.

This patch adds hacks for both, as a demonstration of what's required.
Hopefully we can do better... but this is better than nothing.

Author: efriedma-quic

llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp

@@ -1278,12 +1278,14 @@ void CodeViewDebug::collectVariableInfoFromMFTable(
         TFI->getFrameIndexReference(*Asm->MF, VI.getStackSlot(), FrameReg);
     uint16_t CVReg = TRI->getCodeViewRegNum(FrameReg);
 
-    assert(!FrameOffset.getScalable() &&
-           "Frame offsets with a scalable component are not supported");
+    // FIXME: Assume the scale factor is one, to avoid crashing. We can fix
+    // once we have information on the correct encoding.
+    uint64_t FrameOffsetFixed =
+        FrameOffset.getFixed() + FrameOffset.getScalable();
 
     // Calculate the label ranges.
     LocalVarDef DefRange =
-        createDefRangeMem(CVReg, FrameOffset.getFixed() + ExprOffset);
+        createDefRangeMem(CVReg, FrameOffsetFixed + ExprOffset);
 
     LocalVariable Var;
     Var.DIVar = VI.Var;

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

@@ -298,6 +298,41 @@ void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
       {codeview::RegisterId::ARM64_H29, AArch64::H29},
       {codeview::RegisterId::ARM64_H30, AArch64::H30},
       {codeview::RegisterId::ARM64_H31, AArch64::H31},
+      // FIXME: Temporarily map Z registers using Q register IDs until we
+      // get the actual numbers.
+      {codeview::RegisterId::ARM64_Q0, AArch64::Z0},
+      {codeview::RegisterId::ARM64_Q1, AArch64::Z1},
+      {codeview::RegisterId::ARM64_Q2, AArch64::Z2},
+      {codeview::RegisterId::ARM64_Q3, AArch64::Z3},
+      {codeview::RegisterId::ARM64_Q4, AArch64::Z4},
+      {codeview::RegisterId::ARM64_Q5, AArch64::Z5},
+      {codeview::RegisterId::ARM64_Q6, AArch64::Z6},
+      {codeview::RegisterId::ARM64_Q7, AArch64::Z7},
+      {codeview::RegisterId::ARM64_Q8, AArch64::Z8},
+      {codeview::RegisterId::ARM64_Q9, AArch64::Z9},
+      {codeview::RegisterId::ARM64_Q10, AArch64::Z10},
+      {codeview::RegisterId::ARM64_Q11, AArch64::Z11},
+      {codeview::RegisterId::ARM64_Q12, AArch64::Z12},
+      {codeview::RegisterId::ARM64_Q13, AArch64::Z13},
+      {codeview::RegisterId::ARM64_Q14, AArch64::Z14},
+      {codeview::RegisterId::ARM64_Q15, AArch64::Z15},
+      {codeview::RegisterId::ARM64_Q16, AArch64::Z16},
+      {codeview::RegisterId::ARM64_Q17, AArch64::Z17},
+      {codeview::RegisterId::ARM64_Q18, AArch64::Z18},
+      {codeview::RegisterId::ARM64_Q19, AArch64::Z19},
+      {codeview::RegisterId::ARM64_Q20, AArch64::Z20},
+      {codeview::RegisterId::ARM64_Q21, AArch64::Z21},
+      {codeview::RegisterId::ARM64_Q22, AArch64::Z22},
+      {codeview::RegisterId::ARM64_Q23, AArch64::Z23},
+      {codeview::RegisterId::ARM64_Q24, AArch64::Z24},
+      {codeview::RegisterId::ARM64_Q25, AArch64::Z25},
+      {codeview::RegisterId::ARM64_Q26, AArch64::Z26},
+      {codeview::RegisterId::ARM64_Q27, AArch64::Z27},
+      {codeview::RegisterId::ARM64_Q28, AArch64::Z28},
+      {codeview::RegisterId::ARM64_Q29, AArch64::Z29},
+      {codeview::RegisterId::ARM64_Q30, AArch64::Z30},
+      {codeview::RegisterId::ARM64_Q31, AArch64::Z31},
+
   };
   for (const auto &I : RegMap)
     MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));