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[MC] Make MCParsedAsmOperand::getReg() return MCRegister (#86444)
1 parent 2e4e04c commit 5e5b656

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24 files changed

+46
-39
lines changed

24 files changed

+46
-39
lines changed

‎llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515

1616
namespace llvm {
1717

18+
class MCRegister;
1819
class raw_ostream;
1920

2021
/// MCParsedAsmOperand - This abstract class represents a source-level assembly
@@ -57,7 +58,7 @@ class MCParsedAsmOperand {
5758
virtual bool isImm() const = 0;
5859
/// isReg - Is this a register operand?
5960
virtual bool isReg() const = 0;
60-
virtual unsigned getReg() const = 0;
61+
virtual MCRegister getReg() const = 0;
6162

6263
/// isMem - Is this a memory operand?
6364
virtual bool isMem() const = 0;

‎llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -514,9 +514,7 @@ class MCTargetAsmParser : public MCAsmParserExtension {
514514
/// by the tied-operands checks in the AsmMatcher. This method can be
515515
/// overridden to allow e.g. a sub- or super-register as the tied operand.
516516
virtual bool areEqualRegs(const MCParsedAsmOperand &Op1,
517-
const MCParsedAsmOperand &Op2) const {
518-
return Op1.isReg() && Op2.isReg() && Op1.getReg() == Op2.getReg();
519-
}
517+
const MCParsedAsmOperand &Op2) const;
520518

521519
// Return whether this parser uses assignment statements with equals tokens
522520
virtual bool equalIsAsmAssignment() { return true; };

‎llvm/lib/MC/MCParser/MCTargetAsmParser.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88

99
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
1010
#include "llvm/MC/MCContext.h"
11+
#include "llvm/MC/MCRegister.h"
1112

1213
using namespace llvm;
1314

@@ -48,3 +49,8 @@ ParseStatus MCTargetAsmParser::parseDirective(AsmToken DirectiveID) {
4849
return ParseStatus::Failure;
4950
return ParseStatus::NoMatch;
5051
}
52+
53+
bool MCTargetAsmParser::areEqualRegs(const MCParsedAsmOperand &Op1,
54+
const MCParsedAsmOperand &Op2) const {
55+
return Op1.isReg() && Op2.isReg() && Op1.getReg() == Op2.getReg();
56+
}

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -654,7 +654,7 @@ class AArch64Operand : public MCParsedAsmOperand {
654654
return Barrier.HasnXSModifier;
655655
}
656656

657-
unsigned getReg() const override {
657+
MCRegister getReg() const override {
658658
assert(Kind == k_Register && "Invalid access!");
659659
return Reg.RegNum;
660660
}

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -981,7 +981,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
981981
return Imm.Type;
982982
}
983983

984-
unsigned getReg() const override {
984+
MCRegister getReg() const override {
985985
assert(isRegKind());
986986
return Reg.RegNo;
987987
}

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1002,7 +1002,7 @@ class ARMOperand : public MCParsedAsmOperand {
10021002
return StringRef(Tok.Data, Tok.Length);
10031003
}
10041004

1005-
unsigned getReg() const override {
1005+
MCRegister getReg() const override {
10061006
assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
10071007
return Reg.RegNum;
10081008
}

‎llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,7 @@ class AVROperand : public MCParsedAsmOperand {
195195
return Tok;
196196
}
197197

198-
unsigned getReg() const override {
198+
MCRegister getReg() const override {
199199
assert((Kind == k_Register || Kind == k_Memri) && "Invalid access!");
200200

201201
return RegImm.Reg;

‎llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ struct BPFOperand : public MCParsedAsmOperand {
148148
/// getEndLoc - Gets location of the last token of this operand
149149
SMLoc getEndLoc() const override { return EndLoc; }
150150

151-
unsigned getReg() const override {
151+
MCRegister getReg() const override {
152152
assert(Kind == Register && "Invalid type access!");
153153
return Reg.RegNum;
154154
}

‎llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -400,7 +400,7 @@ struct CSKYOperand : public MCParsedAsmOperand {
400400
/// Gets location of the last token of this operand.
401401
SMLoc getEndLoc() const override { return EndLoc; }
402402

403-
unsigned getReg() const override {
403+
MCRegister getReg() const override {
404404
assert(Kind == Register && "Invalid type access!");
405405
return Reg.RegNum;
406406
}

‎llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,7 @@ struct HexagonOperand : public MCParsedAsmOperand {
245245
/// getEndLoc - Get the location of the last token of this operand.
246246
SMLoc getEndLoc() const override { return EndLoc; }
247247

248-
unsigned getReg() const override {
248+
MCRegister getReg() const override {
249249
assert(Kind == Register && "Invalid access!");
250250
return Reg.RegNum;
251251
}

‎llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,7 @@ struct LanaiOperand : public MCParsedAsmOperand {
151151
// getEndLoc - Gets location of the last token of this operand
152152
SMLoc getEndLoc() const override { return EndLoc; }
153153

154-
unsigned getReg() const override {
154+
MCRegister getReg() const override {
155155
assert(isReg() && "Invalid type access!");
156156
return Reg.RegNum;
157157
}

‎llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -467,9 +467,9 @@ class LoongArchOperand : public MCParsedAsmOperand {
467467
/// Gets location of the last token of this operand.
468468
SMLoc getEndLoc() const override { return EndLoc; }
469469

470-
unsigned getReg() const override {
470+
MCRegister getReg() const override {
471471
assert(Kind == KindTy::Register && "Invalid type access!");
472-
return Reg.RegNum.id();
472+
return Reg.RegNum;
473473
}
474474

475475
const MCExpr *getImm() const {

‎llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -157,7 +157,7 @@ class M68kOperand : public MCParsedAsmOperand {
157157
bool isDReg() const;
158158
bool isFPDReg() const;
159159
bool isFPCReg() const;
160-
unsigned getReg() const override;
160+
MCRegister getReg() const override;
161161
void addRegOperands(MCInst &Inst, unsigned N) const;
162162

163163
static std::unique_ptr<M68kOperand> createMemOp(M68kMemOp MemOp, SMLoc Start,
@@ -312,7 +312,7 @@ bool M68kOperand::isReg() const {
312312
return Kind == KindTy::MemOp && MemOp.Op == M68kMemOp::Kind::Reg;
313313
}
314314

315-
unsigned M68kOperand::getReg() const {
315+
MCRegister M68kOperand::getReg() const {
316316
assert(isReg());
317317
return MemOp.OuterReg;
318318
}

‎llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -183,7 +183,7 @@ class MSP430Operand : public MCParsedAsmOperand {
183183
return Tok;
184184
}
185185

186-
unsigned getReg() const override {
186+
MCRegister getReg() const override {
187187
assert(Kind == k_Reg && "Invalid access!");
188188
return Reg;
189189
}

‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1458,7 +1458,7 @@ class MipsOperand : public MCParsedAsmOperand {
14581458
return StringRef(Tok.Data, Tok.Length);
14591459
}
14601460

1461-
unsigned getReg() const override {
1461+
MCRegister getReg() const override {
14621462
// As a special case until we sort out the definition of div/divu, accept
14631463
// $0/$zero here so that MCK_ZERO works correctly.
14641464
if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&

‎llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -276,9 +276,11 @@ struct PPCOperand : public MCParsedAsmOperand {
276276
return TLSReg.Sym;
277277
}
278278

279-
unsigned getReg() const override {
279+
MCRegister getReg() const override { llvm_unreachable("Not implemented"); }
280+
281+
unsigned getRegNum() const {
280282
assert(isRegNumber() && "Invalid access!");
281-
return (unsigned) Imm.Val;
283+
return (unsigned)Imm.Val;
282284
}
283285

284286
unsigned getFpReg() const {
@@ -459,22 +461,22 @@ struct PPCOperand : public MCParsedAsmOperand {
459461

460462
void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
461463
assert(N == 1 && "Invalid number of operands!");
462-
Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
464+
Inst.addOperand(MCOperand::createReg(RRegs[getRegNum()]));
463465
}
464466

465467
void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
466468
assert(N == 1 && "Invalid number of operands!");
467-
Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
469+
Inst.addOperand(MCOperand::createReg(RRegsNoR0[getRegNum()]));
468470
}
469471

470472
void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
471473
assert(N == 1 && "Invalid number of operands!");
472-
Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
474+
Inst.addOperand(MCOperand::createReg(XRegs[getRegNum()]));
473475
}
474476

475477
void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
476478
assert(N == 1 && "Invalid number of operands!");
477-
Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
479+
Inst.addOperand(MCOperand::createReg(XRegsNoX0[getRegNum()]));
478480
}
479481

480482
void addRegG8pRCOperands(MCInst &Inst, unsigned N) const {
@@ -498,12 +500,12 @@ struct PPCOperand : public MCParsedAsmOperand {
498500

499501
void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
500502
assert(N == 1 && "Invalid number of operands!");
501-
Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
503+
Inst.addOperand(MCOperand::createReg(FRegs[getRegNum()]));
502504
}
503505

504506
void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
505507
assert(N == 1 && "Invalid number of operands!");
506-
Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
508+
Inst.addOperand(MCOperand::createReg(FRegs[getRegNum()]));
507509
}
508510

509511
void addRegFpRCOperands(MCInst &Inst, unsigned N) const {
@@ -513,12 +515,12 @@ struct PPCOperand : public MCParsedAsmOperand {
513515

514516
void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
515517
assert(N == 1 && "Invalid number of operands!");
516-
Inst.addOperand(MCOperand::createReg(VFRegs[getReg()]));
518+
Inst.addOperand(MCOperand::createReg(VFRegs[getRegNum()]));
517519
}
518520

519521
void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
520522
assert(N == 1 && "Invalid number of operands!");
521-
Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
523+
Inst.addOperand(MCOperand::createReg(VRegs[getRegNum()]));
522524
}
523525

524526
void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
@@ -538,12 +540,12 @@ struct PPCOperand : public MCParsedAsmOperand {
538540

539541
void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const {
540542
assert(N == 1 && "Invalid number of operands!");
541-
Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
543+
Inst.addOperand(MCOperand::createReg(RRegs[getRegNum()]));
542544
}
543545

544546
void addRegSPERCOperands(MCInst &Inst, unsigned N) const {
545547
assert(N == 1 && "Invalid number of operands!");
546-
Inst.addOperand(MCOperand::createReg(SPERegs[getReg()]));
548+
Inst.addOperand(MCOperand::createReg(SPERegs[getRegNum()]));
547549
}
548550

549551
void addRegACCRCOperands(MCInst &Inst, unsigned N) const {

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -977,9 +977,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
977977
return Imm.IsRV64;
978978
}
979979

980-
unsigned getReg() const override {
980+
MCRegister getReg() const override {
981981
assert(Kind == KindTy::Register && "Invalid type access!");
982-
return Reg.RegNum.id();
982+
return Reg.RegNum;
983983
}
984984

985985
StringRef getSysReg() const {

‎llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -307,7 +307,7 @@ class SparcOperand : public MCParsedAsmOperand {
307307
return StringRef(Tok.Data, Tok.Length);
308308
}
309309

310-
unsigned getReg() const override {
310+
MCRegister getReg() const override {
311311
assert((Kind == k_Register) && "Invalid access!");
312312
return Reg.RegNum;
313313
}

‎llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -227,7 +227,7 @@ class SystemZOperand : public MCParsedAsmOperand {
227227
bool isReg(RegisterKind RegKind) const {
228228
return Kind == KindReg && Reg.Kind == RegKind;
229229
}
230-
unsigned getReg() const override {
230+
MCRegister getReg() const override {
231231
assert(Kind == KindReg && "Not a register");
232232
return Reg.Num;
233233
}

‎llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -344,7 +344,7 @@ class VEOperand : public MCParsedAsmOperand {
344344
return StringRef(Tok.Data, Tok.Length);
345345
}
346346

347-
unsigned getReg() const override {
347+
MCRegister getReg() const override {
348348
assert((Kind == k_Register) && "Invalid access!");
349349
return Reg.RegNum;
350350
}

‎llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ struct WebAssemblyOperand : public MCParsedAsmOperand {
100100
bool isReg() const override { return false; }
101101
bool isBrList() const { return Kind == BrList; }
102102

103-
unsigned getReg() const override {
103+
MCRegister getReg() const override {
104104
llvm_unreachable("Assembly inspects a register operand");
105105
return 0;
106106
}

‎llvm/lib/Target/X86/AsmParser/X86Operand.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,7 @@ struct X86Operand final : public MCParsedAsmOperand {
167167
Tok.Length = Value.size();
168168
}
169169

170-
unsigned getReg() const override {
170+
MCRegister getReg() const override {
171171
assert(Kind == Register && "Invalid access!");
172172
return Reg.RegNo;
173173
}

‎llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ struct XtensaOperand : public MCParsedAsmOperand {
244244
/// getEndLoc - Gets location of the last token of this operand
245245
SMLoc getEndLoc() const override { return EndLoc; }
246246

247-
unsigned getReg() const override {
247+
MCRegister getReg() const override {
248248
assert(Kind == Register && "Invalid type access!");
249249
return Reg.RegNum;
250250
}

‎llvm/utils/TableGen/AsmMatcherEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2519,7 +2519,7 @@ static void emitValidateOperandClass(AsmMatcherInfo &Info, raw_ostream &OS) {
25192519
// Check for register operands, including sub-classes.
25202520
OS << " if (Operand.isReg()) {\n";
25212521
OS << " MatchClassKind OpKind;\n";
2522-
OS << " switch (Operand.getReg()) {\n";
2522+
OS << " switch (Operand.getReg().id()) {\n";
25232523
OS << " default: OpKind = InvalidMatchClass; break;\n";
25242524
for (const auto &RC : Info.RegisterClasses)
25252525
OS << " case " << RC.first->getValueAsString("Namespace")

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