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[SLP][NFC]Add a test, producing serie of extrtactelements, building non-extendable tree
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-grtev4-linux-gnu -mattr="+aes,+avx,+cmov,+crc32,+cx16,+cx8,+fxsr,+mmx,+pclmul,+popcnt,+prfchw,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" < %s | FileCheck %s
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define void @test(i64 %v) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: i64 [[V:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[BB:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> <i64 0, i64 poison>, i64 [[V]], i32 1
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; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i64> zeroinitializer, [[TMP0]]
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; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
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; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 0, [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 0, 0
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; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP3]], [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 0, 0
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; CHECK-NEXT: [[TMP7:%.*]] = and i1 [[TMP5]], [[TMP6]]
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; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 0, 0
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; CHECK-NEXT: [[TMP9:%.*]] = and i1 [[TMP7]], [[TMP8]]
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; CHECK-NEXT: [[TMP10:%.*]] = and i1 [[TMP9]], false
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; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 0, [[TMP2]]
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; CHECK-NEXT: [[TMP12:%.*]] = and i1 [[TMP10]], [[TMP11]]
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; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 0, 0
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; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP12]], [[TMP13]]
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; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 0, 0
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; CHECK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
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; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 0, 0
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; CHECK-NEXT: [[TMP18:%.*]] = and i1 [[TMP16]], [[TMP17]]
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; CHECK-NEXT: [[TMP19:%.*]] = icmp ult i64 0, 0
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; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i1 [[TMP18]], i1 false
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; CHECK-NEXT: br i1 [[TMP20]], label %[[BB_I107_PREHEADER:.*]], label %[[BB_I27_I_PREHEADER:.*]]
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; CHECK: [[BB_I107_PREHEADER]]:
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; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
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; CHECK-NEXT: [[DOTSROA_1278_10_EXTRACT_SHIFT83_I1622_1:%.*]] = xor i64 0, [[TMP21]]
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; CHECK-NEXT: [[TMP22:%.*]] = xor <2 x i64> zeroinitializer, [[TMP1]]
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; CHECK-NEXT: [[TMP23:%.*]] = or <2 x i64> [[TMP22]], zeroinitializer
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; CHECK-NEXT: [[TMP24:%.*]] = or <2 x i64> splat (i64 1), [[TMP23]]
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; CHECK-NEXT: [[TMP25:%.*]] = and <2 x i64> [[TMP24]], zeroinitializer
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; CHECK-NEXT: [[TMP26:%.*]] = icmp eq <2 x i64> [[TMP25]], zeroinitializer
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; CHECK-NEXT: ret void
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; CHECK: [[BB_I27_I_PREHEADER]]:
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; CHECK-NEXT: unreachable
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;
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bb:
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%.sroa.82529.14.insert.insert = or i64 0, 0
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%.sroa.02528.sroa.0.0.insert.insert = or i64 %v, 0
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%0 = icmp eq i64 0, %.sroa.02528.sroa.0.0.insert.insert
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%1 = icmp eq i64 0, 0
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%2 = and i1 %0, %1
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%3 = icmp eq i64 0, 0
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%4 = and i1 %2, %3
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%5 = icmp eq i64 0, 0
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%6 = and i1 %4, %5
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%7 = and i1 %6, false
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%8 = icmp eq i64 0, %.sroa.02528.sroa.0.0.insert.insert
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%9 = and i1 %7, %8
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%10 = icmp eq i64 0, 0
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%11 = and i1 %9, %10
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%12 = icmp eq i64 0, 0
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%13 = and i1 %11, %12
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%14 = icmp eq i64 0, 0
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%15 = and i1 %13, %14
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%16 = icmp ult i64 0, 0
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%17 = select i1 %16, i1 %15, i1 false
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br i1 %17, label %bb.i107.preheader, label %bb.i27.i.preheader
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bb.i107.preheader: ; preds = %bb
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%.sroa.1278.10.extract.shift83.i1622.1 = xor i64 0, %.sroa.82529.14.insert.insert
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%.sroa.076.2.extract.shift80.i1619.4 = xor i64 0, %.sroa.02528.sroa.0.0.insert.insert
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%.sroa.071.2.extract.shift86.i1625.4 = or i64 %.sroa.076.2.extract.shift80.i1619.4, 0
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%.sroa.1278.10.extract.shift83.i1622.7 = xor i64 0, %.sroa.82529.14.insert.insert
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%.sroa.12.10.extract.shift89.i1634.7 = or i64 %.sroa.1278.10.extract.shift83.i1622.7, 0
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%.sroa.02756.2.extract.shift6530 = or i64 %.sroa.071.2.extract.shift86.i1625.4, 1
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%18 = and i64 %.sroa.02756.2.extract.shift6530, 0
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%19 = icmp eq i64 %18, 0
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%20 = or i64 1, %.sroa.12.10.extract.shift89.i1634.7
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%21 = and i64 %20, 0
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%22 = icmp eq i64 %21, 0
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ret void
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bb.i27.i.preheader: ; preds = %bb
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unreachable
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}
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