|
| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-grtev4-linux-gnu -mattr="+aes,+avx,+cmov,+crc32,+cx16,+cx8,+fxsr,+mmx,+pclmul,+popcnt,+prfchw,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" < %s | FileCheck %s |
| 3 | + |
| 4 | +define void @test(i64 %v) { |
| 5 | +; CHECK-LABEL: define void @test( |
| 6 | +; CHECK-SAME: i64 [[V:%.*]]) #[[ATTR0:[0-9]+]] { |
| 7 | +; CHECK-NEXT: [[BB:.*:]] |
| 8 | +; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> <i64 0, i64 poison>, i64 [[V]], i32 1 |
| 9 | +; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i64> zeroinitializer, [[TMP0]] |
| 10 | +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1 |
| 11 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 0, [[TMP2]] |
| 12 | +; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 0, 0 |
| 13 | +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP3]], [[TMP4]] |
| 14 | +; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 0, 0 |
| 15 | +; CHECK-NEXT: [[TMP7:%.*]] = and i1 [[TMP5]], [[TMP6]] |
| 16 | +; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 0, 0 |
| 17 | +; CHECK-NEXT: [[TMP9:%.*]] = and i1 [[TMP7]], [[TMP8]] |
| 18 | +; CHECK-NEXT: [[TMP10:%.*]] = and i1 [[TMP9]], false |
| 19 | +; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 0, [[TMP2]] |
| 20 | +; CHECK-NEXT: [[TMP12:%.*]] = and i1 [[TMP10]], [[TMP11]] |
| 21 | +; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 0, 0 |
| 22 | +; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP12]], [[TMP13]] |
| 23 | +; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 0, 0 |
| 24 | +; CHECK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]] |
| 25 | +; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 0, 0 |
| 26 | +; CHECK-NEXT: [[TMP18:%.*]] = and i1 [[TMP16]], [[TMP17]] |
| 27 | +; CHECK-NEXT: [[TMP19:%.*]] = icmp ult i64 0, 0 |
| 28 | +; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i1 [[TMP18]], i1 false |
| 29 | +; CHECK-NEXT: br i1 [[TMP20]], label %[[BB_I107_PREHEADER:.*]], label %[[BB_I27_I_PREHEADER:.*]] |
| 30 | +; CHECK: [[BB_I107_PREHEADER]]: |
| 31 | +; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0 |
| 32 | +; CHECK-NEXT: [[DOTSROA_1278_10_EXTRACT_SHIFT83_I1622_1:%.*]] = xor i64 0, [[TMP21]] |
| 33 | +; CHECK-NEXT: [[TMP22:%.*]] = xor <2 x i64> zeroinitializer, [[TMP1]] |
| 34 | +; CHECK-NEXT: [[TMP23:%.*]] = or <2 x i64> [[TMP22]], zeroinitializer |
| 35 | +; CHECK-NEXT: [[TMP24:%.*]] = or <2 x i64> splat (i64 1), [[TMP23]] |
| 36 | +; CHECK-NEXT: [[TMP25:%.*]] = and <2 x i64> [[TMP24]], zeroinitializer |
| 37 | +; CHECK-NEXT: [[TMP26:%.*]] = icmp eq <2 x i64> [[TMP25]], zeroinitializer |
| 38 | +; CHECK-NEXT: ret void |
| 39 | +; CHECK: [[BB_I27_I_PREHEADER]]: |
| 40 | +; CHECK-NEXT: unreachable |
| 41 | +; |
| 42 | +bb: |
| 43 | + %.sroa.82529.14.insert.insert = or i64 0, 0 |
| 44 | + %.sroa.02528.sroa.0.0.insert.insert = or i64 %v, 0 |
| 45 | + %0 = icmp eq i64 0, %.sroa.02528.sroa.0.0.insert.insert |
| 46 | + %1 = icmp eq i64 0, 0 |
| 47 | + %2 = and i1 %0, %1 |
| 48 | + %3 = icmp eq i64 0, 0 |
| 49 | + %4 = and i1 %2, %3 |
| 50 | + %5 = icmp eq i64 0, 0 |
| 51 | + %6 = and i1 %4, %5 |
| 52 | + %7 = and i1 %6, false |
| 53 | + %8 = icmp eq i64 0, %.sroa.02528.sroa.0.0.insert.insert |
| 54 | + %9 = and i1 %7, %8 |
| 55 | + %10 = icmp eq i64 0, 0 |
| 56 | + %11 = and i1 %9, %10 |
| 57 | + %12 = icmp eq i64 0, 0 |
| 58 | + %13 = and i1 %11, %12 |
| 59 | + %14 = icmp eq i64 0, 0 |
| 60 | + %15 = and i1 %13, %14 |
| 61 | + %16 = icmp ult i64 0, 0 |
| 62 | + %17 = select i1 %16, i1 %15, i1 false |
| 63 | + br i1 %17, label %bb.i107.preheader, label %bb.i27.i.preheader |
| 64 | + |
| 65 | +bb.i107.preheader: ; preds = %bb |
| 66 | + %.sroa.1278.10.extract.shift83.i1622.1 = xor i64 0, %.sroa.82529.14.insert.insert |
| 67 | + %.sroa.076.2.extract.shift80.i1619.4 = xor i64 0, %.sroa.02528.sroa.0.0.insert.insert |
| 68 | + %.sroa.071.2.extract.shift86.i1625.4 = or i64 %.sroa.076.2.extract.shift80.i1619.4, 0 |
| 69 | + %.sroa.1278.10.extract.shift83.i1622.7 = xor i64 0, %.sroa.82529.14.insert.insert |
| 70 | + %.sroa.12.10.extract.shift89.i1634.7 = or i64 %.sroa.1278.10.extract.shift83.i1622.7, 0 |
| 71 | + %.sroa.02756.2.extract.shift6530 = or i64 %.sroa.071.2.extract.shift86.i1625.4, 1 |
| 72 | + %18 = and i64 %.sroa.02756.2.extract.shift6530, 0 |
| 73 | + %19 = icmp eq i64 %18, 0 |
| 74 | + %20 = or i64 1, %.sroa.12.10.extract.shift89.i1634.7 |
| 75 | + %21 = and i64 %20, 0 |
| 76 | + %22 = icmp eq i64 %21, 0 |
| 77 | + ret void |
| 78 | + |
| 79 | +bb.i27.i.preheader: ; preds = %bb |
| 80 | + unreachable |
| 81 | +} |
| 82 | + |
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