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Revert "[RISCV] Support Zama16b1p0 (#88474)"
This reverts commit b090569.
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‎clang/test/Preprocessor/riscv-target-features.c

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@@ -79,7 +79,6 @@
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// CHECK-NOT: __riscv_za128rs {{.*$}}
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// CHECK-NOT: __riscv_za64rs {{.*$}}
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// CHECK-NOT: __riscv_zacas {{.*$}}
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// CHECK-NOT: __riscv_zama16b {{.*$}}
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// CHECK-NOT: __riscv_zawrs {{.*$}}
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// CHECK-NOT: __riscv_zba {{.*$}}
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// CHECK-NOT: __riscv_zbb {{.*$}}
@@ -705,12 +704,6 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
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// CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}}
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// RUN: %clang --target=riscv32 -march=rv32izama16b -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZAMA16B-EXT %s
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// RUN: %clang --target=riscv64 -march=rv64izama16b -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZAMA16B-EXT %s
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// CHECK-ZAMA16B-EXT: __riscv_zama16b 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32izawrs -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZAWRS-EXT %s

‎llvm/docs/RISCVUsage.rst

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@@ -119,7 +119,6 @@ on support follow.
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``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
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``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
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``Zacas`` Supported (`See note <#riscv-zacas-note>`__)
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``Zama16b`` Supported (`See note <#riscv-profiles-extensions-note>`__)
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``Zawrs`` Assembly Support
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``Zba`` Supported
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``Zbb`` Supported
@@ -238,7 +237,7 @@ Supported
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.. _riscv-profiles-extensions-note:
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``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare``
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``Za128rs``, ``Za64rs``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare``
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These extensions are defined as part of the `RISC-V Profiles specification <https://github.com/riscv/riscv-profiles/releases/tag/v1.0>`__. They do not introduce any new features themselves, but instead describe existing hardware features.
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.. _riscv-zacas-note:

‎llvm/lib/Support/RISCVISAInfo.cpp

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@@ -119,7 +119,6 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
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{"za128rs", {1, 0}},
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{"za64rs", {1, 0}},
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{"zacas", {1, 0}},
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{"zama16b", {1, 0}},
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{"zawrs", {1, 0}},
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{"zba", {1, 0}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -208,13 +208,6 @@ def HasStdExtAOrZalrsc
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"'A' (Atomic Instructions) or "
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"'Zalrsc' (Load-Reserved/Store-Conditional)">;
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def FeatureStdExtZama16b
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: SubtargetFeature<"zama16b", "HasStdExtZama16b", "true",
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"'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
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def HasStdExtZama16b : Predicate<"Subtarget->hasStdExtZama16b()">,
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AssemblerPredicate<(all_of FeatureStdExtZama16b),
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"'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
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def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
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"'Zawrs' (Wait on Reservation Set)">;
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def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -115,7 +115,6 @@
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; RUN: llc -mtriple=riscv32 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
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; RUN: llc -mtriple=riscv32 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV32ZAMA16B %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zabha %s -o - | FileCheck --check-prefix=RV32ZABHA %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssnpm %s -o - | FileCheck --check-prefix=RV32SSNPM %s
@@ -200,7 +199,6 @@
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
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; RUN: llc -mtriple=riscv64 -mattr=+za64rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA64RS %s
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; RUN: llc -mtriple=riscv64 -mattr=+za128rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA128RS %s
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; RUN: llc -mtriple=riscv64 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAMA16B %s
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; RUN: llc -mtriple=riscv64 -mattr=+zawrs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAWRS %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefixes=CHECK,RV64ZTSO %s
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; RUN: llc -mtriple=riscv64 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
@@ -372,7 +370,6 @@
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; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
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; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1"
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; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc0p2"
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; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0"
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; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4"
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; RV32ZABHA: .attribute 5, "rv32i2p1_a2p1_zabha1p0"
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; RV32SSNPM: .attribute 5, "rv32i2p1_ssnpm0p8"
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; RV64ZICBOZ: .attribute 5, "rv64i2p1_zicboz1p0"
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; RV64ZA64RS: .attribute 5, "rv64i2p1_za64rs1p0"
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; RV64ZA128RS: .attribute 5, "rv64i2p1_za128rs1p0"
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; RV64ZAMA16B: .attribute 5, "rv64i2p1_zama16b1p0"
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; RV64ZAWRS: .attribute 5, "rv64i2p1_zawrs1p0"
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; RV64ZICBOP: .attribute 5, "rv64i2p1_zicbop1p0"
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; RV64SHCOUNTERENW: .attribute 5, "rv64i2p1_shcounterenw1p0"

‎llvm/test/MC/RISCV/attribute-arch.s

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.attribute arch, "rv32iza64rs1p0"
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# CHECK: attribute 5, "rv32i2p1_za64rs1p0"
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.attribute arch, "rv32izama16b"
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# CHECK: attribute 5, "rv32i2p1_zama16b1p0"
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.attribute arch, "rv32izawrs1p0"
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# CHECK: attribute 5, "rv32i2p1_zawrs1p0"
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‎llvm/unittests/Support/RISCVISAInfoTest.cpp

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@@ -769,7 +769,6 @@ R"(All available -march extensions for RISC-V
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za128rs 1.0
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za64rs 1.0
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zacas 1.0
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zama16b 1.0
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zawrs 1.0
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zfa 1.0
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zfh 1.0

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