@@ -1483,7 +1483,7 @@ define <8 x i16> @fptos_v8f64_v8i16(<8 x double> %a) {
14831483; CHECK-SD-NEXT: adrp x8, .LCPI70_0
14841484; CHECK-SD-NEXT: fcvtzs v1.2d, v1.2d
14851485; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
1486- ; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI54_0 ]
1486+ ; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI70_0 ]
14871487; CHECK-SD-NEXT: xtn v3.2s, v3.2d
14881488; CHECK-SD-NEXT: xtn v2.2s, v2.2d
14891489; CHECK-SD-NEXT: xtn v1.2s, v1.2d
@@ -1514,7 +1514,7 @@ define <8 x i16> @fptou_v8f64_v8i16(<8 x double> %a) {
15141514; CHECK-SD-NEXT: adrp x8, .LCPI71_0
15151515; CHECK-SD-NEXT: fcvtzs v1.2d, v1.2d
15161516; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
1517- ; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI55_0 ]
1517+ ; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI71_0 ]
15181518; CHECK-SD-NEXT: xtn v3.2s, v3.2d
15191519; CHECK-SD-NEXT: xtn v2.2s, v2.2d
15201520; CHECK-SD-NEXT: xtn v1.2s, v1.2d
@@ -1545,7 +1545,7 @@ define <16 x i16> @fptos_v16f64_v16i16(<16 x double> %a) {
15451545; CHECK-SD-NEXT: adrp x8, .LCPI72_0
15461546; CHECK-SD-NEXT: fcvtzs v2.2d, v2.2d
15471547; CHECK-SD-NEXT: fcvtzs v6.2d, v6.2d
1548- ; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI56_0 ]
1548+ ; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI72_0 ]
15491549; CHECK-SD-NEXT: fcvtzs v1.2d, v1.2d
15501550; CHECK-SD-NEXT: fcvtzs v5.2d, v5.2d
15511551; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
@@ -1592,7 +1592,7 @@ define <16 x i16> @fptou_v16f64_v16i16(<16 x double> %a) {
15921592; CHECK-SD-NEXT: adrp x8, .LCPI73_0
15931593; CHECK-SD-NEXT: fcvtzs v2.2d, v2.2d
15941594; CHECK-SD-NEXT: fcvtzs v6.2d, v6.2d
1595- ; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI57_0 ]
1595+ ; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI73_0 ]
15961596; CHECK-SD-NEXT: fcvtzs v1.2d, v1.2d
15971597; CHECK-SD-NEXT: fcvtzs v5.2d, v5.2d
15981598; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
@@ -1656,7 +1656,7 @@ define <32 x i16> @fptos_v32f64_v32i16(<32 x double> %a) {
16561656; CHECK-SD-NEXT: fcvtzs v16.2d, v16.2d
16571657; CHECK-SD-NEXT: xtn v3.2s, v3.2d
16581658; CHECK-SD-NEXT: xtn v2.2s, v2.2d
1659- ; CHECK-SD-NEXT: adrp x8, .LCPI58_0
1659+ ; CHECK-SD-NEXT: adrp x8, .LCPI74_0
16601660; CHECK-SD-NEXT: xtn v1.2s, v1.2d
16611661; CHECK-SD-NEXT: xtn v0.2s, v0.2d
16621662; CHECK-SD-NEXT: xtn v7.2s, v7.2d
@@ -1671,7 +1671,7 @@ define <32 x i16> @fptos_v32f64_v32i16(<32 x double> %a) {
16711671; CHECK-SD-NEXT: xtn v4.2s, v4.2d
16721672; CHECK-SD-NEXT: xtn v18.2s, v22.2d
16731673; CHECK-SD-NEXT: xtn v22.2s, v16.2d
1674- ; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI58_0 ]
1674+ ; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI74_0 ]
16751675; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v16.16b
16761676; CHECK-SD-NEXT: tbl v1.16b, { v4.16b, v5.16b, v6.16b, v7.16b }, v16.16b
16771677; CHECK-SD-NEXT: tbl v2.16b, { v18.16b, v19.16b, v20.16b, v21.16b }, v16.16b
@@ -1743,7 +1743,7 @@ define <32 x i16> @fptou_v32f64_v32i16(<32 x double> %a) {
17431743; CHECK-SD-NEXT: fcvtzs v16.2d, v16.2d
17441744; CHECK-SD-NEXT: xtn v3.2s, v3.2d
17451745; CHECK-SD-NEXT: xtn v2.2s, v2.2d
1746- ; CHECK-SD-NEXT: adrp x8, .LCPI59_0
1746+ ; CHECK-SD-NEXT: adrp x8, .LCPI75_0
17471747; CHECK-SD-NEXT: xtn v1.2s, v1.2d
17481748; CHECK-SD-NEXT: xtn v0.2s, v0.2d
17491749; CHECK-SD-NEXT: xtn v7.2s, v7.2d
@@ -1758,7 +1758,7 @@ define <32 x i16> @fptou_v32f64_v32i16(<32 x double> %a) {
17581758; CHECK-SD-NEXT: xtn v4.2s, v4.2d
17591759; CHECK-SD-NEXT: xtn v18.2s, v22.2d
17601760; CHECK-SD-NEXT: xtn v22.2s, v16.2d
1761- ; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI59_0 ]
1761+ ; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI75_0 ]
17621762; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v16.16b
17631763; CHECK-SD-NEXT: tbl v1.16b, { v4.16b, v5.16b, v6.16b, v7.16b }, v16.16b
17641764; CHECK-SD-NEXT: tbl v2.16b, { v18.16b, v19.16b, v20.16b, v21.16b }, v16.16b
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