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AArch64+GISel: legalize vector remainder operations.
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2 files changed

+140
-41
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2 files changed

+140
-41
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‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
169169
.scalarize(0);
170170

171171
getActionDefinitionsBuilder({G_SREM, G_UREM, G_SDIVREM, G_UDIVREM})
172-
.lowerFor({s1, s8, s16, s32, s64});
172+
.lowerFor({s1, s8, s16, s32, s64, v2s64, v4s32, v2s32})
173+
.widenScalarOrEltToNextPow2(0)
174+
.clampScalarOrElt(0, s32, s64)
175+
.clampNumElements(0, v2s32, v4s32)
176+
.clampNumElements(0, v2s64, v2s64)
177+
.moreElementsToNextPow2(0);
178+
173179

174180
getActionDefinitionsBuilder({G_SMULO, G_UMULO})
175181
.widenScalarToNextPow2(0, /*Min = */ 32)

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir

Lines changed: 133 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,11 @@ body: |
66
bb.0.entry:
77
; CHECK-LABEL: name: test_urem_64
88
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
9-
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
10-
; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
11-
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
12-
; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[MUL]]
13-
; CHECK: $x0 = COPY [[SUB]](s64)
9+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
10+
; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
11+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
12+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[MUL]]
13+
; CHECK-NEXT: $x0 = COPY [[SUB]](s64)
1414
%0:_(s64) = COPY $x0
1515
%1:_(s64) = COPY $x1
1616
%2:_(s64) = G_UREM %0, %1
@@ -23,13 +23,13 @@ body: |
2323
bb.0.entry:
2424
; CHECK-LABEL: name: test_srem_32
2525
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
26-
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
27-
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
28-
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
29-
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
30-
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC1]]
31-
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[MUL]]
32-
; CHECK: $w0 = COPY [[SUB]](s32)
26+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
27+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
28+
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
29+
; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
30+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC1]]
31+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[MUL]]
32+
; CHECK-NEXT: $w0 = COPY [[SUB]](s32)
3333
%0:_(s64) = COPY $x0
3434
%1:_(s64) = COPY $x1
3535
%2:_(s32) = G_TRUNC %0(s64)
@@ -44,17 +44,17 @@ body: |
4444
bb.0.entry:
4545
; CHECK-LABEL: name: test_srem_8
4646
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
47-
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
48-
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
49-
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
50-
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
51-
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
52-
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
53-
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
54-
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC2]]
55-
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
56-
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[MUL]]
57-
; CHECK: $w0 = COPY [[SUB]](s32)
47+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
48+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
49+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
50+
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
51+
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
52+
; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
53+
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
54+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC2]]
55+
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
56+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[MUL]]
57+
; CHECK-NEXT: $w0 = COPY [[SUB]](s32)
5858
%0:_(s64) = COPY $x0
5959
%1:_(s64) = COPY $x1
6060
%2:_(s8) = G_TRUNC %0(s64)
@@ -70,23 +70,23 @@ body: |
7070
bb.0.entry:
7171
; CHECK-LABEL: name: test_frem
7272
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
73-
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
74-
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
75-
; CHECK: $d0 = COPY [[COPY]](s64)
76-
; CHECK: $d1 = COPY [[COPY1]](s64)
77-
; CHECK: BL &fmod, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
78-
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
79-
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
80-
; CHECK: $x0 = COPY [[COPY2]](s64)
81-
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
82-
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
83-
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
84-
; CHECK: $s0 = COPY [[TRUNC]](s32)
85-
; CHECK: $s1 = COPY [[TRUNC1]](s32)
86-
; CHECK: BL &fmodf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
87-
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
88-
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
89-
; CHECK: $w0 = COPY [[COPY3]](s32)
73+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
74+
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
75+
; CHECK-NEXT: $d0 = COPY [[COPY]](s64)
76+
; CHECK-NEXT: $d1 = COPY [[COPY1]](s64)
77+
; CHECK-NEXT: BL &fmod, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
78+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
79+
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
80+
; CHECK-NEXT: $x0 = COPY [[COPY2]](s64)
81+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
82+
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
83+
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
84+
; CHECK-NEXT: $s0 = COPY [[TRUNC]](s32)
85+
; CHECK-NEXT: $s1 = COPY [[TRUNC1]](s32)
86+
; CHECK-NEXT: BL &fmodf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
87+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
88+
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
89+
; CHECK-NEXT: $w0 = COPY [[COPY3]](s32)
9090
%0:_(s64) = COPY $x0
9191
%1:_(s64) = COPY $x1
9292
%2:_(s64) = G_FREM %0, %1
@@ -97,3 +97,96 @@ body: |
9797
$w0 = COPY %5(s32)
9898
9999
...
100+
---
101+
name: test_srem_v2s32
102+
body: |
103+
bb.0.entry:
104+
; CHECK-LABEL: name: test_srem_v2s32
105+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
106+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
107+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
108+
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
109+
; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[UV]], [[UV2]]
110+
; CHECK-NEXT: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[UV1]], [[UV3]]
111+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SDIV]](s32), [[SDIV1]](s32)
112+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x s32>) = G_MUL [[BUILD_VECTOR]], [[COPY1]]
113+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<2 x s32>) = G_SUB [[COPY]], [[MUL]]
114+
; CHECK-NEXT: $d0 = COPY [[SUB]](<2 x s32>)
115+
%0:_(<2 x s32>) = COPY $d0
116+
%1:_(<2 x s32>) = COPY $d1
117+
%2:_(<2 x s32>) = G_SREM %0, %1
118+
$d0 = COPY %2(<2 x s32>)
119+
120+
...
121+
---
122+
name: test_srem_v4s32
123+
body: |
124+
bb.0.entry:
125+
; CHECK-LABEL: name: test_srem_v4s32
126+
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
127+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
128+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
129+
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
130+
; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[UV]], [[UV4]]
131+
; CHECK-NEXT: [[UDIV1:%[0-9]+]]:_(s32) = G_UDIV [[UV1]], [[UV5]]
132+
; CHECK-NEXT: [[UDIV2:%[0-9]+]]:_(s32) = G_UDIV [[UV2]], [[UV6]]
133+
; CHECK-NEXT: [[UDIV3:%[0-9]+]]:_(s32) = G_UDIV [[UV3]], [[UV7]]
134+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UDIV]](s32), [[UDIV1]](s32), [[UDIV2]](s32), [[UDIV3]](s32)
135+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[BUILD_VECTOR]], [[COPY1]]
136+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[COPY]], [[MUL]]
137+
; CHECK-NEXT: $q0 = COPY [[SUB]](<4 x s32>)
138+
%0:_(<4 x s32>) = COPY $q0
139+
%1:_(<4 x s32>) = COPY $q1
140+
%2:_(<4 x s32>) = G_UREM %0, %1
141+
$q0 = COPY %2(<4 x s32>)
142+
143+
...
144+
---
145+
name: test_srem_v2s64
146+
body: |
147+
bb.0.entry:
148+
; CHECK-LABEL: name: test_srem_v2s64
149+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
150+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
151+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
152+
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
153+
; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[UV]], [[UV2]]
154+
; CHECK-NEXT: [[SDIV1:%[0-9]+]]:_(s64) = G_SDIV [[UV1]], [[UV3]]
155+
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
156+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SDIV]], [[UV4]]
157+
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SDIV1]], [[UV5]]
158+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MUL]](s64), [[MUL1]](s64)
159+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[COPY]], [[BUILD_VECTOR]]
160+
; CHECK-NEXT: $q0 = COPY [[SUB]](<2 x s64>)
161+
%0:_(<2 x s64>) = COPY $q0
162+
%1:_(<2 x s64>) = COPY $q1
163+
%2:_(<2 x s64>) = G_SREM %0, %1
164+
$q0 = COPY %2(<2 x s64>)
165+
166+
...
167+
---
168+
name: test_srem_v4s16
169+
body: |
170+
bb.0.entry:
171+
; CHECK-LABEL: name: test_srem_v4s16
172+
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
173+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
174+
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
175+
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY1]](<4 x s16>)
176+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT]](<4 x s32>)
177+
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT1]](<4 x s32>)
178+
; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[UV]], [[UV4]]
179+
; CHECK-NEXT: [[UDIV1:%[0-9]+]]:_(s32) = G_UDIV [[UV1]], [[UV5]]
180+
; CHECK-NEXT: [[UDIV2:%[0-9]+]]:_(s32) = G_UDIV [[UV2]], [[UV6]]
181+
; CHECK-NEXT: [[UDIV3:%[0-9]+]]:_(s32) = G_UDIV [[UV3]], [[UV7]]
182+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UDIV]](s32), [[UDIV1]](s32), [[UDIV2]](s32), [[UDIV3]](s32)
183+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[BUILD_VECTOR]], [[ZEXT1]]
184+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[ZEXT]], [[MUL]]
185+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[SUB]](<4 x s32>)
186+
; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)
187+
%0:_(<4 x s16>) = COPY $d0
188+
%1:_(<4 x s16>) = COPY $d1
189+
%2:_(<4 x s16>) = G_UREM %0, %1
190+
$d0 = COPY %2(<4 x s16>)
191+
192+
...

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