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RISCVAsmParser: Make diagnostics more conventional
Most diagnostics obey https://llvm.org/docs/CodingStandards.html#error-and-warning-messages but some diverge. Fix them. While here, adjust some diagnostics. Pull Request: #92024
1 parent 344c73e commit 5f7477a

13 files changed

+189
-190
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 23 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -2829,12 +2829,12 @@ bool RISCVAsmParser::parseDirectiveOption() {
28292829

28302830
if (isDigit(Arch.back()))
28312831
return Error(
2832-
Loc, "Extension version number parsing not currently implemented");
2832+
Loc, "extension version number parsing not currently implemented");
28332833

28342834
std::string Feature = RISCVISAInfo::getTargetFeatureForExtension(Arch);
28352835
if (!enableExperimentalExtension() &&
28362836
StringRef(Feature).starts_with("experimental-"))
2837-
return Error(Loc, "Unexpected experimental extensions.");
2837+
return Error(Loc, "unexpected experimental extensions");
28382838
auto Ext = llvm::lower_bound(RISCVFeatureKV, Feature);
28392839
if (Ext == std::end(RISCVFeatureKV) || StringRef(Ext->Key) != Feature)
28402840
return Error(Loc, "unknown extension feature");
@@ -2866,10 +2866,10 @@ bool RISCVAsmParser::parseDirectiveOption() {
28662866
for (auto &Feature : RISCVFeatureKV) {
28672867
if (getSTI().hasFeature(Feature.Value) &&
28682868
Feature.Implies.test(Ext->Value))
2869-
return Error(Loc,
2870-
Twine("Can't disable ") + Ext->Key + " extension, " +
2871-
Feature.Key + " extension requires " + Ext->Key +
2872-
" extension be enabled");
2869+
return Error(Loc, Twine("can't disable ") + Ext->Key +
2870+
" extension; " + Feature.Key +
2871+
" extension requires " + Ext->Key +
2872+
" extension");
28732873
}
28742874

28752875
clearFeatureBits(Ext->Value, Ext->Key);
@@ -3382,8 +3382,8 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
33823382
unsigned TempReg = Inst.getOperand(1).getReg();
33833383
if (DestReg == TempReg) {
33843384
SMLoc Loc = Operands.back()->getStartLoc();
3385-
return Error(Loc, "The temporary vector register cannot be the same as "
3386-
"the destination register.");
3385+
return Error(Loc, "the temporary vector register cannot be the same as "
3386+
"the destination register");
33873387
}
33883388
}
33893389

@@ -3395,8 +3395,7 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
33953395
// The encoding with rd1 == rd2 == rs1 is reserved for XTHead load pair.
33963396
if (Rs1 == Rd1 && Rs1 == Rd2) {
33973397
SMLoc Loc = Operands[1]->getStartLoc();
3398-
return Error(Loc, "The source register and destination registers "
3399-
"cannot be equal.");
3398+
return Error(Loc, "rs1, rd1, and rd2 cannot all be the same");
34003399
}
34013400
}
34023401

@@ -3405,7 +3404,7 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
34053404
unsigned Rd2 = Inst.getOperand(1).getReg();
34063405
if (Rd1 == Rd2) {
34073406
SMLoc Loc = Operands[1]->getStartLoc();
3408-
return Error(Loc, "'rs1' and 'rs2' must be different.");
3407+
return Error(Loc, "rs1 and rs2 must be different");
34093408
}
34103409
}
34113410

@@ -3416,10 +3415,10 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
34163415
// depending on the data width.
34173416
if (IsTHeadMemPair32 && Inst.getOperand(4).getImm() != 3) {
34183417
SMLoc Loc = Operands.back()->getStartLoc();
3419-
return Error(Loc, "Operand must be constant 3.");
3418+
return Error(Loc, "operand must be constant 3");
34203419
} else if (IsTHeadMemPair64 && Inst.getOperand(4).getImm() != 4) {
34213420
SMLoc Loc = Operands.back()->getStartLoc();
3422-
return Error(Loc, "Operand must be constant 4.");
3421+
return Error(Loc, "operand must be constant 4");
34233422
}
34243423

34253424
const MCInstrDesc &MCID = MII.get(Opcode);
@@ -3434,14 +3433,14 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
34343433
if (MCID.TSFlags & RISCVII::VS1Constraint) {
34353434
unsigned VCIXRs1 = Inst.getOperand(Inst.getNumOperands() - 1).getReg();
34363435
if (VCIXDst == VCIXRs1)
3437-
return Error(VCIXDstLoc, "The destination vector register group cannot"
3438-
" overlap the source vector register group.");
3436+
return Error(VCIXDstLoc, "the destination vector register group cannot"
3437+
" overlap the source vector register group");
34393438
}
34403439
if (MCID.TSFlags & RISCVII::VS2Constraint) {
34413440
unsigned VCIXRs2 = Inst.getOperand(Inst.getNumOperands() - 2).getReg();
34423441
if (VCIXDst == VCIXRs2)
3443-
return Error(VCIXDstLoc, "The destination vector register group cannot"
3444-
" overlap the source vector register group.");
3442+
return Error(VCIXDstLoc, "the destination vector register group cannot"
3443+
" overlap the source vector register group");
34453444
}
34463445
return false;
34473446
}
@@ -3457,14 +3456,14 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
34573456
if (MCID.TSFlags & RISCVII::VS2Constraint) {
34583457
unsigned CheckReg = Inst.getOperand(Offset + 1).getReg();
34593458
if (DestReg == CheckReg)
3460-
return Error(Loc, "The destination vector register group cannot overlap"
3461-
" the source vector register group.");
3459+
return Error(Loc, "the destination vector register group cannot overlap"
3460+
" the source vector register group");
34623461
}
34633462
if ((MCID.TSFlags & RISCVII::VS1Constraint) && Inst.getOperand(Offset + 2).isReg()) {
34643463
unsigned CheckReg = Inst.getOperand(Offset + 2).getReg();
34653464
if (DestReg == CheckReg)
3466-
return Error(Loc, "The destination vector register group cannot overlap"
3467-
" the source vector register group.");
3465+
return Error(Loc, "the destination vector register group cannot overlap"
3466+
" the source vector register group");
34683467
}
34693468
if ((MCID.TSFlags & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) {
34703469
// vadc, vsbc are special cases. These instructions have no mask register.
@@ -3474,7 +3473,7 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
34743473
Opcode == RISCV::VSBC_VXM || Opcode == RISCV::VFMERGE_VFM ||
34753474
Opcode == RISCV::VMERGE_VIM || Opcode == RISCV::VMERGE_VVM ||
34763475
Opcode == RISCV::VMERGE_VXM)
3477-
return Error(Loc, "The destination vector register group cannot be V0.");
3476+
return Error(Loc, "the destination vector register group cannot be V0");
34783477

34793478
// Regardless masked or unmasked version, the number of operands is the
34803479
// same. For example, "viota.m v0, v2" is "viota.m v0, v2, NoRegister"
@@ -3485,8 +3484,8 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
34853484
"Unexpected register for mask operand");
34863485

34873486
if (DestReg == CheckReg)
3488-
return Error(Loc, "The destination vector register group cannot overlap"
3489-
" the mask register.");
3487+
return Error(Loc, "the destination vector register group cannot overlap"
3488+
" the mask register");
34903489
}
34913490
return false;
34923491
}

‎llvm/test/MC/RISCV/option-invalid.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34,14 +34,14 @@
3434
# CHECK: :[[#@LINE+1]]:18: error: expected comma
3535
.option arch, +c foo
3636

37-
# CHECK: :[[#@LINE+1]]:16: error: Extension version number parsing not currently implemented
37+
# CHECK: :[[#@LINE+1]]:16: error: extension version number parsing not currently implemented
3838
.option arch, +c2p0
3939

4040
.option arch, +d
41-
# CHECK: :[[#@LINE+1]]:16: error: Can't disable f extension, d extension requires f extension be enabled
41+
# CHECK: :[[#@LINE+1]]:16: error: can't disable f extension; d extension requires f extension
4242
.option arch, -f
4343

44-
# CHECK: :[[#@LINE+1]]:16: error: Can't disable zicsr extension, f extension requires zicsr extension be enabled
44+
# CHECK: :[[#@LINE+1]]:16: error: can't disable zicsr extension; f extension requires zicsr extension
4545
.option arch, -zicsr
4646

4747
# CHECK: :[[#@LINE+1]]:20: error: 'f' and 'zfinx' extensions are incompatible

‎llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,13 @@ th.sdd a0, a1, (a2) # CHECK: [[@LINE]]:1: error: too few operands for in
88
th.sdd a0, a1, (a2), 3, 5 # CHECK: [[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
99
th.lwud t0, t1, (t2), 5, 4 # CHECK: [[@LINE]]:23: error: immediate must be an integer in the range [0, 3]
1010
th.lwud t0, t1, (t2) # CHECK: [[@LINE]]:1: error: too few operands for instruction
11-
th.lwud t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:26: error: Operand must be constant 3.
11+
th.lwud t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:26: error: operand must be constant 3
1212
th.lwd a3, a4, (a5), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
1313
th.lwd a3, a4, (a5) # CHECK: [[@LINE]]:1: error: too few operands for instruction
14-
th.lwd a3, a4, (a5), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 3.
14+
th.lwd a3, a4, (a5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 3
1515
th.swd t3, t4, (t5), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
1616
th.swd t3, t4, (t5) # CHECK: [[@LINE]]:1: error: too few operands for instruction
17-
th.swd t3, t4, (t5), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 3.
18-
th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: The source register and destination registers cannot be equal.
17+
th.swd t3, t4, (t5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 3
18+
th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: rs1, rd1, and rd2 cannot all be the same
1919
th.ldd t0, t1, (t2), 2, 4 # CHECK: [[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
2020
th.sdd t0, t1, (t2), 2, 4 # CHECK: [[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}

‎llvm/test/MC/RISCV/rv32zcmp-invalid.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
# CHECK-ERROR: error: invalid operand for instruction
55
cm.mvsa01 a1, a2
66

7-
# CHECK-ERROR: error: 'rs1' and 'rs2' must be different
7+
# CHECK-ERROR: error: rs1 and rs2 must be different
88
cm.mvsa01 s0, s0
99

1010
# CHECK-ERROR: error: invalid operand for instruction

‎llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,17 +2,17 @@
22

33
th.ldd t0, t1, (t2), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
44
th.ldd t0, t1, (t2) # CHECK: [[@LINE]]:1: error: too few operands for instruction
5-
th.ldd t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 4.
5+
th.ldd t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 4
66
th.sdd a0, a1, (a2), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
77
th.sdd a0, a1, (a2) # CHECK: [[@LINE]]:1: error: too few operands for instruction
8-
th.sdd a0, a1, (a2), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 4.
8+
th.sdd a0, a1, (a2), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 4
99
th.lwud t0, t1, (t2), 5, 4 # CHECK: [[@LINE]]:23: error: immediate must be an integer in the range [0, 3]
1010
th.lwud t0, t1, (t2) # CHECK: [[@LINE]]:1: error: too few operands for instruction
11-
th.lwud t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:26: error: Operand must be constant 3.
11+
th.lwud t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:26: error: operand must be constant 3
1212
th.lwd a3, a4, (a5), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
1313
th.lwd a3, a4, (a5) # CHECK: [[@LINE]]:1: error: too few operands for instruction
14-
th.lwd a3, a4, (a5), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 3.
14+
th.lwd a3, a4, (a5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 3
1515
th.swd t3, t4, (t5), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
1616
th.swd t3, t4, (t5) # CHECK: [[@LINE]]:1: error: too few operands for instruction
17-
th.swd t3, t4, (t5), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 3.
18-
th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: The source register and destination registers cannot be equal.
17+
th.swd t3, t4, (t5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 3
18+
th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: rs1, rd1, and rd2 cannot all be the same

‎llvm/test/MC/RISCV/rv64zcmp-invalid.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
# CHECK-ERROR: error: invalid operand for instruction
55
cm.mvsa01 a1, a2
66

7-
# CHECK-ERROR: error: 'rs1' and 'rs2' must be different
7+
# CHECK-ERROR: error: rs1 and rs2 must be different
88
cm.mvsa01 s0, s0
99

1010
# CHECK-ERROR: error: invalid operand for instruction

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