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[CodeGen] Remove static member function Register::isPhysicalRegister. NFC
Prefer the nonstatic member by converting unsigned to Register instead.
1 parent b0210fe commit 5fadb3d

16 files changed

+32
-39
lines changed

‎llvm/include/llvm/CodeGen/RDFRegisters.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,7 @@ struct RegisterRef {
111111
}
112112

113113
static constexpr bool isRegId(unsigned Id) {
114-
return Register::isPhysicalRegister(Id);
114+
return Register(Id).isPhysical();
115115
}
116116
static constexpr bool isUnitId(unsigned Id) {
117117
return Register(Id).isVirtual();

‎llvm/include/llvm/CodeGen/Register.h

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -48,12 +48,6 @@ class Register {
4848
return Register(FI + MCRegister::FirstStackSlot);
4949
}
5050

51-
/// Return true if the specified register number is in
52-
/// the physical register namespace.
53-
static constexpr bool isPhysicalRegister(unsigned Reg) {
54-
return MCRegister::isPhysicalRegister(Reg);
55-
}
56-
5751
/// Convert a 0-based index to a virtual register number.
5852
/// This is the inverse operation of VirtReg2IndexFunctor below.
5953
static Register index2VirtReg(unsigned Index) {
@@ -67,7 +61,9 @@ class Register {
6761

6862
/// Return true if the specified register number is in the physical register
6963
/// namespace.
70-
constexpr bool isPhysical() const { return isPhysicalRegister(Reg); }
64+
constexpr bool isPhysical() const {
65+
return MCRegister::isPhysicalRegister(Reg);
66+
}
7167

7268
/// Convert a virtual register number to a 0-based index. The first virtual
7369
/// register in a function will get the index 0.

‎llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -525,7 +525,7 @@ void llvm::calculateDbgEntityHistory(const MachineFunction *MF,
525525
// Don't consider SP to be clobbered by register masks.
526526
for (auto It : RegVars) {
527527
unsigned int Reg = It.first;
528-
if (Reg != SP && Register::isPhysicalRegister(Reg) &&
528+
if (Reg != SP && Register(Reg).isPhysical() &&
529529
MO.clobbersPhysReg(Reg))
530530
RegsToClobber.push_back(Reg);
531531
}

‎llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -564,7 +564,7 @@ DIE &DwarfCompileUnit::updateSubprogramScopeDIE(const DISubprogram *SP,
564564
TFI->getDwarfFrameBase(*Asm->MF);
565565
switch (FrameBase.Kind) {
566566
case TargetFrameLowering::DwarfFrameBase::Register: {
567-
if (Register::isPhysicalRegister(FrameBase.Location.Reg)) {
567+
if (Register(FrameBase.Location.Reg).isPhysical()) {
568568
MachineLocation Location(FrameBase.Location.Reg);
569569
addAddress(*SPDie, dwarf::DW_AT_frame_base, Location);
570570
}

‎llvm/lib/CodeGen/LiveRangeCalc.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -216,7 +216,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
216216
report_fatal_error("Use not jointly dominated by defs.");
217217
}
218218

219-
if (Register::isPhysicalRegister(PhysReg)) {
219+
if (Register(PhysReg).isPhysical()) {
220220
const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
221221
bool IsLiveIn = MBB->isLiveIn(PhysReg);
222222
for (MCRegAliasIterator Alias(PhysReg, TRI, false); !IsLiveIn && Alias.isValid(); ++Alias)

‎llvm/lib/CodeGen/MachineScheduler.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3966,8 +3966,7 @@ void GenericScheduler::reschedulePhysReg(SUnit *SU, bool isTop) {
39663966
// Find already scheduled copies with a single physreg dependence and move
39673967
// them just above the scheduled instruction.
39683968
for (SDep &Dep : Deps) {
3969-
if (Dep.getKind() != SDep::Data ||
3970-
!Register::isPhysicalRegister(Dep.getReg()))
3969+
if (Dep.getKind() != SDep::Data || !Register(Dep.getReg()).isPhysical())
39713970
continue;
39723971
SUnit *DepSU = Dep.getSUnit();
39733972
if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)

‎llvm/lib/CodeGen/RegAllocFast.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -708,7 +708,7 @@ void RegAllocFastImpl::reloadAtBegin(MachineBasicBlock &MBB) {
708708
/// not used by a virtreg. Kill the physreg, marking it free. This may add
709709
/// implicit kills to MO->getParent() and invalidate MO.
710710
bool RegAllocFastImpl::usePhysReg(MachineInstr &MI, MCPhysReg Reg) {
711-
assert(Register::isPhysicalRegister(Reg) && "expected physreg");
711+
assert(Register(Reg).isPhysical() && "expected physreg");
712712
bool displacedAny = displacePhysReg(MI, Reg);
713713
setPhysRegState(Reg, regPreAssigned);
714714
markRegUsedInInstr(Reg);
@@ -1289,7 +1289,7 @@ void RegAllocFastImpl::dumpState() const {
12891289
assert(VirtReg.isVirtual() && "Bad map key");
12901290
MCPhysReg PhysReg = LR.PhysReg;
12911291
if (PhysReg != 0) {
1292-
assert(Register::isPhysicalRegister(PhysReg) && "mapped to physreg");
1292+
assert(Register(PhysReg).isPhysical() && "mapped to physreg");
12931293
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
12941294
assert(RegUnitStates[Unit] == VirtReg && "inverse map valid");
12951295
}

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -501,8 +501,8 @@ bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
501501
F.isClobberKind()) {
502502
// Check for def of register or earlyclobber register.
503503
for (; NumVals; --NumVals, ++i) {
504-
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
505-
if (Register::isPhysicalRegister(Reg))
504+
Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
505+
if (Reg.isPhysical())
506506
CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
507507
}
508508
} else

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10125,9 +10125,8 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
1012510125
auto DetectWriteToReservedRegister = [&]() {
1012610126
const MachineFunction &MF = DAG.getMachineFunction();
1012710127
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
10128-
for (unsigned Reg : OpInfo.AssignedRegs.Regs) {
10129-
if (Register::isPhysicalRegister(Reg) &&
10130-
TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
10128+
for (Register Reg : OpInfo.AssignedRegs.Regs) {
10129+
if (Reg.isPhysical() && TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
1013110130
const char *RegName = TRI.getName(Reg);
1013210131
emitInlineAsmError(Call, "write to reserved register '" +
1013310132
Twine(RegName) + "'");
@@ -11389,7 +11388,7 @@ void SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V,
1138911388
assert((Op.getOpcode() != ISD::CopyFromReg ||
1139011389
cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
1139111390
"Copy from a reg to the same reg!");
11392-
assert(!Register::isPhysicalRegister(Reg) && "Is a physreg");
11391+
assert(!Register(Reg).isPhysical() && "Is a physreg");
1139311392

1139411393
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1139511394
// If this is an InlineAsm we have to match the registers required, not the

‎llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -155,11 +155,11 @@ bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd,
155155

156156
LiveIntervals &LIs = G.getMetadata().LIS;
157157

158-
if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) {
159-
LLVM_DEBUG(dbgs() << "Rd is a physical reg:"
160-
<< Register::isPhysicalRegister(Rd) << '\n');
161-
LLVM_DEBUG(dbgs() << "Ra is a physical reg:"
162-
<< Register::isPhysicalRegister(Ra) << '\n');
158+
if (Register(Rd).isPhysical() || Register(Ra).isPhysical()) {
159+
LLVM_DEBUG(dbgs() << "Rd is a physical reg:" << Register(Rd).isPhysical()
160+
<< '\n');
161+
LLVM_DEBUG(dbgs() << "Ra is a physical reg:" << Register(Ra).isPhysical()
162+
<< '\n');
163163
return false;
164164
}
165165

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1108,7 +1108,7 @@ ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
11081108
if (!SubIdx)
11091109
return MIB.addReg(Reg, State);
11101110

1111-
if (Register::isPhysicalRegister(Reg))
1111+
if (Register(Reg).isPhysical())
11121112
return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
11131113
return MIB.addReg(Reg, State, SubIdx);
11141114
}

‎llvm/lib/Target/ARM/ARMLatencyMutations.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -802,7 +802,7 @@ signed M85Overrides::modifyMixedWidthFP(const MachineInstr *SrcMI,
802802
OP.getSubReg() == ARM::ssub_1)
803803
return 1;
804804
}
805-
} else if (Register::isPhysicalRegister(RegID)) {
805+
} else if (Register(RegID).isPhysical()) {
806806
// Note that when the producer is narrower, not all of the producers
807807
// may be present in the scheduling graph; somewhere earlier in the
808808
// compiler, an implicit def/use of the aliased full register gets

‎llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -223,8 +223,8 @@ static bool areCombinableOperations(const TargetRegisterInfo *TRI,
223223
return true;
224224
}
225225

226-
static bool isEvenReg(unsigned Reg) {
227-
assert(Register::isPhysicalRegister(Reg));
226+
static bool isEvenReg(Register Reg) {
227+
assert(Reg.isPhysical());
228228
if (Hexagon::IntRegsRegClass.contains(Reg))
229229
return (Reg - Hexagon::R0) % 2 == 0;
230230
if (Hexagon::HvxVRRegClass.contains(Reg))
@@ -546,7 +546,7 @@ MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1,
546546
// is even.
547547
bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
548548
bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
549-
unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
549+
Register FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
550550
if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex))
551551
continue;
552552

‎llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -275,7 +275,7 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
275275
return false;
276276
}
277277

278-
unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
278+
Register cmpReg1, cmpOp2;
279279
cmpReg1 = MI.getOperand(1).getReg();
280280

281281
if (secondReg) {
@@ -290,7 +290,7 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
290290
// at machine code level, we don't need this, but if we decide
291291
// to move new value jump prior to RA, we would be needing this.
292292
MachineRegisterInfo &MRI = MF.getRegInfo();
293-
if (!Register::isPhysicalRegister(cmpOp2)) {
293+
if (!cmpOp2.isPhysical()) {
294294
MachineInstr *def = MRI.getVRegDef(cmpOp2);
295295
if (def->getOpcode() == TargetOpcode::COPY)
296296
return false;
@@ -480,7 +480,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
480480
bool foundJump = false;
481481
bool foundCompare = false;
482482
bool invertPredicate = false;
483-
unsigned predReg = 0; // predicate reg of the jump.
483+
Register predReg; // predicate reg of the jump.
484484
unsigned cmpReg1 = 0;
485485
int cmpOp2 = 0;
486486
MachineBasicBlock::iterator jmpPos;
@@ -516,7 +516,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
516516
jmpPos = MII;
517517
jmpInstr = &MI;
518518
predReg = MI.getOperand(0).getReg();
519-
afterRA = Register::isPhysicalRegister(predReg);
519+
afterRA = predReg.isPhysical();
520520

521521
// If ifconverter had not messed up with the kill flags of the
522522
// operands, the following check on the kill flag would suffice.

‎llvm/lib/Target/Hexagon/RDFCopy.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,8 @@ bool CopyPropagation::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) {
4444
const MachineOperand &Src = MI->getOperand(1);
4545
RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg());
4646
RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());
47-
assert(Register::isPhysicalRegister(DstR.Reg));
48-
assert(Register::isPhysicalRegister(SrcR.Reg));
47+
assert(Register(DstR.Reg).isPhysical());
48+
assert(Register(SrcR.Reg).isPhysical());
4949
const TargetRegisterInfo &TRI = DFG.getTRI();
5050
if (TRI.getMinimalPhysRegClass(DstR.Reg) !=
5151
TRI.getMinimalPhysRegClass(SrcR.Reg))

‎llvm/lib/Target/M68k/M68kRegisterInfo.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,8 +83,7 @@ M68kRegisterInfo::getMatchingMegaReg(unsigned Reg,
8383

8484
const TargetRegisterClass *
8585
M68kRegisterInfo::getMaximalPhysRegClass(unsigned reg, MVT VT) const {
86-
assert(Register::isPhysicalRegister(reg) &&
87-
"reg must be a physical register");
86+
assert(Register(reg).isPhysical() && "reg must be a physical register");
8887

8988
// Pick the most sub register class of the right type that contains
9089
// this physreg.

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