[PowerPC][SelectionDAG] Expand @llvm.copysign.ppc_fp128 without copysignl

workingjubilee · workingjubilee · commit 5fd0d86737fa · 2024-10-31T17:35:25.000-07:00
This allows ripping out the remaining copysignl infra.
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.def b/llvm/include/llvm/IR/RuntimeLibcalls.def
@@ -289,7 +289,6 @@ HANDLE_LIBCALL(FLOOR_F64, "floor")
 HANDLE_LIBCALL(FLOOR_F80, "floorl")
 HANDLE_LIBCALL(FLOOR_F128, "floorl")
 HANDLE_LIBCALL(FLOOR_PPCF128, "floorl")
-HANDLE_LIBCALL(COPYSIGN_PPCF128, "copysignl")
 HANDLE_LIBCALL(FMIN_F32, "fminf")
 HANDLE_LIBCALL(FMIN_F64, "fmin")
 HANDLE_LIBCALL(FMIN_F80, "fminl")
diff --git a/llvm/lib/CodeGen/IntrinsicLowering.cpp b/llvm/lib/CodeGen/IntrinsicLowering.cpp
@@ -437,18 +437,6 @@ void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
     ReplaceFPIntrinsicWithCall(CI, "roundevenf", "roundeven", "roundevenl");
     break;
   }
-  case Intrinsic::copysign: {
-    switch (CI->getArgOperand(0)->getType()->getTypeID()) {
-    default:
-      report_fatal_error("copysign intrinsic without arch-specific floats "
-                         "reached intrinsic-to-libcall lowering");
-      break;
-    case Type::PPC_FP128TyID:
-      ReplaceCallWith("copysignl", CI, CI->arg_begin(), CI->arg_end(),
-                      Type::getFloatTy(CI->getContext()));
-    }
-    break;
-  }
   case Intrinsic::get_rounding:
      // Lower to "round to the nearest"
      if (!CI->getType()->isVoidTy())
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -1710,11 +1710,18 @@ void DAGTypeLegalizer::ExpandFloatRes_FCEIL(SDNode *N,
 void DAGTypeLegalizer::ExpandFloatRes_FCOPYSIGN(SDNode *N,
                                                 SDValue &Lo, SDValue &Hi) {
 
-  EVT VT = N->getValueType(0);
-  ExpandFloatRes_Binary(
-      N,
-      (VT == MVT::ppcf128 ? RTLIB::COPYSIGN_PPCF128 : RTLIB::UNKNOWN_LIBCALL),
-      Lo, Hi);
+  assert(N->getValueType(0) == MVT::ppcf128 &&
+         "Logic only correct for ppcf128!");
+  SDLoc DL = SDLoc(N);
+  SDValue Tmp = SDValue();
+  GetExpandedFloat(N->getOperand(0), Lo, Tmp);
+
+  Hi = DAG.getNode(ISD::FCOPYSIGN, DL, Tmp.getValueType(), Tmp,
+                   N->getOperand(1));
+  // A double-double is Hi + Lo, so if Hi flips sign, so must Lo
+  Lo = DAG.getSelectCC(DL, Tmp, Hi, Lo,
+                       DAG.getNode(ISD::FNEG, DL, Lo.getValueType(), Lo),
+                       ISD::SETEQ);
 }
 
 void DAGTypeLegalizer::ExpandFloatRes_FCOS(SDNode *N,
diff --git a/llvm/test/CodeGen/PowerPC/copysignl.ll b/llvm/test/CodeGen/PowerPC/copysignl.ll
@@ -43,31 +43,26 @@ declare double @copysign(double, double) #0
 define ppc_fp128 @foo_ll(double %a, ppc_fp128 %b) #0 {
 ; CHECK-LABEL: foo_ll:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mflr 0
-; CHECK-NEXT:    stdu 1, -112(1)
-; CHECK-NEXT:    fmr 3, 2
-; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; CHECK-NEXT:    std 0, 128(1)
-; CHECK-NEXT:    lfs 2, .LCPI2_0@toc@l(3)
-; CHECK-NEXT:    bl copysignl
-; CHECK-NEXT:    nop
-; CHECK-NEXT:    addi 1, 1, 112
-; CHECK-NEXT:    ld 0, 16(1)
-; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    fcpsgn 0, 2, 1
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 8
+; CHECK-NEXT:    fcmpu 0, 1, 0
+; CHECK-NEXT:    fmr 1, 0
+; CHECK-NEXT:    iseleq 3, 4, 3
+; CHECK-NEXT:    addis 4, 2, .LCPI2_0@toc@ha
+; CHECK-NEXT:    addi 4, 4, .LCPI2_0@toc@l
+; CHECK-NEXT:    lfdx 2, 4, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-VSX-LABEL: foo_ll:
 ; CHECK-VSX:       # %bb.0: # %entry
-; CHECK-VSX-NEXT:    mflr 0
-; CHECK-VSX-NEXT:    stdu 1, -112(1)
-; CHECK-VSX-NEXT:    fmr 3, 2
+; CHECK-VSX-NEXT:    fmr 0, 1
+; CHECK-VSX-NEXT:    xscpsgndp 1, 2, 1
 ; CHECK-VSX-NEXT:    xxlxor 2, 2, 2
-; CHECK-VSX-NEXT:    std 0, 128(1)
-; CHECK-VSX-NEXT:    bl copysignl
-; CHECK-VSX-NEXT:    nop
-; CHECK-VSX-NEXT:    addi 1, 1, 112
-; CHECK-VSX-NEXT:    ld 0, 16(1)
-; CHECK-VSX-NEXT:    mtlr 0
+; CHECK-VSX-NEXT:    xscmpudp 0, 0, 1
+; CHECK-VSX-NEXT:    beqlr 0
+; CHECK-VSX-NEXT:  # %bb.1: # %entry
+; CHECK-VSX-NEXT:    xsnegdp 2, 2
 ; CHECK-VSX-NEXT:    blr
 entry:
   %conv = fpext double %a to ppc_fp128
@@ -78,31 +73,26 @@ entry:
 define ppc_fp128 @foo_ld(double %a, double %b) #0 {
 ; CHECK-LABEL: foo_ld:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mflr 0
-; CHECK-NEXT:    stdu 1, -112(1)
-; CHECK-NEXT:    fmr 3, 2
-; CHECK-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; CHECK-NEXT:    std 0, 128(1)
-; CHECK-NEXT:    lfs 2, .LCPI3_0@toc@l(3)
-; CHECK-NEXT:    bl copysignl
-; CHECK-NEXT:    nop
-; CHECK-NEXT:    addi 1, 1, 112
-; CHECK-NEXT:    ld 0, 16(1)
-; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    fcpsgn 0, 2, 1
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 8
+; CHECK-NEXT:    fcmpu 0, 1, 0
+; CHECK-NEXT:    fmr 1, 0
+; CHECK-NEXT:    iseleq 3, 4, 3
+; CHECK-NEXT:    addis 4, 2, .LCPI3_0@toc@ha
+; CHECK-NEXT:    addi 4, 4, .LCPI3_0@toc@l
+; CHECK-NEXT:    lfdx 2, 4, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-VSX-LABEL: foo_ld:
 ; CHECK-VSX:       # %bb.0: # %entry
-; CHECK-VSX-NEXT:    mflr 0
-; CHECK-VSX-NEXT:    stdu 1, -112(1)
-; CHECK-VSX-NEXT:    fmr 3, 2
+; CHECK-VSX-NEXT:    fmr 0, 1
+; CHECK-VSX-NEXT:    xscpsgndp 1, 2, 1
 ; CHECK-VSX-NEXT:    xxlxor 2, 2, 2
-; CHECK-VSX-NEXT:    std 0, 128(1)
-; CHECK-VSX-NEXT:    bl copysignl
-; CHECK-VSX-NEXT:    nop
-; CHECK-VSX-NEXT:    addi 1, 1, 112
-; CHECK-VSX-NEXT:    ld 0, 16(1)
-; CHECK-VSX-NEXT:    mtlr 0
+; CHECK-VSX-NEXT:    xscmpudp 0, 0, 1
+; CHECK-VSX-NEXT:    beqlr 0
+; CHECK-VSX-NEXT:  # %bb.1: # %entry
+; CHECK-VSX-NEXT:    xsnegdp 2, 2
 ; CHECK-VSX-NEXT:    blr
 entry:
   %conv = fpext double %a to ppc_fp128
@@ -114,31 +104,26 @@ entry:
 define ppc_fp128 @foo_lf(double %a, float %b) #0 {
 ; CHECK-LABEL: foo_lf:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mflr 0
-; CHECK-NEXT:    stdu 1, -112(1)
-; CHECK-NEXT:    fmr 3, 2
-; CHECK-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-NEXT:    std 0, 128(1)
-; CHECK-NEXT:    lfs 2, .LCPI4_0@toc@l(3)
-; CHECK-NEXT:    bl copysignl
-; CHECK-NEXT:    nop
-; CHECK-NEXT:    addi 1, 1, 112
-; CHECK-NEXT:    ld 0, 16(1)
-; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    fcpsgn 0, 2, 1
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 8
+; CHECK-NEXT:    fcmpu 0, 1, 0
+; CHECK-NEXT:    fmr 1, 0
+; CHECK-NEXT:    iseleq 3, 4, 3
+; CHECK-NEXT:    addis 4, 2, .LCPI4_0@toc@ha
+; CHECK-NEXT:    addi 4, 4, .LCPI4_0@toc@l
+; CHECK-NEXT:    lfdx 2, 4, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-VSX-LABEL: foo_lf:
 ; CHECK-VSX:       # %bb.0: # %entry
-; CHECK-VSX-NEXT:    mflr 0
-; CHECK-VSX-NEXT:    stdu 1, -112(1)
-; CHECK-VSX-NEXT:    fmr 3, 2
+; CHECK-VSX-NEXT:    fmr 0, 1
+; CHECK-VSX-NEXT:    fcpsgn 1, 2, 1
 ; CHECK-VSX-NEXT:    xxlxor 2, 2, 2
-; CHECK-VSX-NEXT:    std 0, 128(1)
-; CHECK-VSX-NEXT:    bl copysignl
-; CHECK-VSX-NEXT:    nop
-; CHECK-VSX-NEXT:    addi 1, 1, 112
-; CHECK-VSX-NEXT:    ld 0, 16(1)
-; CHECK-VSX-NEXT:    mtlr 0
+; CHECK-VSX-NEXT:    xscmpudp 0, 0, 1
+; CHECK-VSX-NEXT:    beqlr 0
+; CHECK-VSX-NEXT:  # %bb.1: # %entry
+; CHECK-VSX-NEXT:    xsnegdp 2, 2
 ; CHECK-VSX-NEXT:    blr
 entry:
   %conv = fpext double %a to ppc_fp128
diff --git a/llvm/test/CodeGen/PowerPC/ctrloop-cpsgn.ll b/llvm/test/CodeGen/PowerPC/ctrloop-cpsgn.ll
@@ -4,84 +4,81 @@
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
 target triple = "powerpc-unknown-linux-gnu"
 
+; Previously we checked that loops that used CTR would not be used around a libm call to copysignl
+; but now that copysignl is no longer emitted by LLVM in most cases, this stands as a tombstone.
+; It has mtctr right in the middle, but we don't care because copysignl is nowhere to be found.
+
 define ppc_fp128 @foo(ptr nocapture %n, ppc_fp128 %d) nounwind readonly {
 ; CHECK-LABEL: foo:
 ; CHECK-NOT: mtctr
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mflr 0
-; CHECK-NEXT:    stwu 1, -176(1)
-; CHECK-NEXT:    stw 0, 180(1)
-; CHECK-NEXT:    stfd 2, 128(1)
-; CHECK-NEXT:    lwz 3, 132(1)
-; CHECK-NEXT:    stfd 1, 136(1)
-; CHECK-NEXT:    stw 3, 148(1)
-; CHECK-NEXT:    lwz 3, 128(1)
-; CHECK-NEXT:    stfd 31, 168(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stw 3, 144(1)
-; CHECK-NEXT:    lwz 3, 140(1)
-; CHECK-NEXT:    lfd 0, 144(1)
-; CHECK-NEXT:    stw 3, 156(1)
-; CHECK-NEXT:    lwz 3, 136(1)
-; CHECK-NEXT:    stw 30, 160(1) # 4-byte Folded Spill
-; CHECK-NEXT:    li 30, 2048
-; CHECK-NEXT:    stw 3, 152(1)
-; CHECK-NEXT:    lfd 31, 152(1)
-; CHECK-NEXT:    fmr 1, 31
+; CHECK-NEXT:    stwu 1, -112(1)
+; CHECK-NEXT:    stfd 2, 80(1)
+; CHECK-NEXT:    li 3, 2048
+; CHECK-NEXT:    lwz 4, 84(1)
+; CHECK-NEXT:    stfd 1, 88(1)
+; CHECK-NEXT:    stw 4, 100(1)
+; CHECK-NEXT:    lwz 4, 80(1)
+; CHECK-NEXT:    stw 4, 96(1)
+; CHECK-NEXT:    lwz 4, 92(1)
+; CHECK-NEXT:    lfd 1, 96(1)
+; CHECK-NEXT:    stw 4, 108(1)
+; CHECK-NEXT:    lwz 4, 88(1)
+; CHECK-NEXT:    stw 4, 104(1)
+; CHECK-NEXT:    lfd 0, 104(1)
+; CHECK-NEXT:    mtctr 3
+; CHECK-NEXT:    fmr 2, 0
+; CHECK-NEXT:    b .LBB0_2
 ; CHECK-NEXT:  .LBB0_1: # %for.body
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stfd 1, 64(1)
-; CHECK-NEXT:    lwz 3, 68(1)
-; CHECK-NEXT:    stfd 31, 88(1)
-; CHECK-NEXT:    stw 3, 84(1)
-; CHECK-NEXT:    lwz 3, 64(1)
-; CHECK-NEXT:    stfd 0, 56(1)
-; CHECK-NEXT:    stw 3, 80(1)
-; CHECK-NEXT:    lwz 3, 92(1)
-; CHECK-NEXT:    lfd 4, 96(1)
-; CHECK-NEXT:    stw 3, 108(1)
-; CHECK-NEXT:    lwz 3, 88(1)
-; CHECK-NEXT:    lfd 1, 80(1)
-; CHECK-NEXT:    stw 3, 104(1)
 ; CHECK-NEXT:    lwz 3, 60(1)
-; CHECK-NEXT:    lfd 3, 104(1)
+; CHECK-NEXT:    stfd 1, 48(1)
 ; CHECK-NEXT:    stw 3, 76(1)
 ; CHECK-NEXT:    lwz 3, 56(1)
 ; CHECK-NEXT:    stw 3, 72(1)
-; CHECK-NEXT:    lfd 2, 72(1)
-; CHECK-NEXT:    bl copysignl
-; CHECK-NEXT:    stfd 2, 48(1)
-; CHECK-NEXT:    addi 30, 30, -1
 ; CHECK-NEXT:    lwz 3, 52(1)
-; CHECK-NEXT:    cmplwi 30, 0
-; CHECK-NEXT:    stfd 1, 40(1)
-; CHECK-NEXT:    stw 3, 116(1)
+; CHECK-NEXT:    lfd 2, 72(1)
+; CHECK-NEXT:    stw 3, 68(1)
 ; CHECK-NEXT:    lwz 3, 48(1)
-; CHECK-NEXT:    stw 3, 112(1)
-; CHECK-NEXT:    lwz 3, 44(1)
-; CHECK-NEXT:    lfd 0, 112(1)
-; CHECK-NEXT:    stw 3, 124(1)
-; CHECK-NEXT:    lwz 3, 40(1)
-; CHECK-NEXT:    stw 3, 120(1)
-; CHECK-NEXT:    lfd 1, 120(1)
-; CHECK-NEXT:    bc 12, 1, .LBB0_1
-; CHECK-NEXT:  # %bb.2: # %for.end
-; CHECK-NEXT:    stfd 1, 16(1)
+; CHECK-NEXT:    stw 3, 64(1)
+; CHECK-NEXT:    lfd 1, 64(1)
+; CHECK-NEXT:    bdz .LBB0_7
+; CHECK-NEXT:  .LBB0_2: # %for.body
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stfd 0, 40(1)
+; CHECK-NEXT:    lbz 3, 40(1)
+; CHECK-NEXT:    srwi 3, 3, 7
+; CHECK-NEXT:    andi. 3, 3, 1
+; CHECK-NEXT:    bc 12, 1, .LBB0_4
+; CHECK-NEXT:  # %bb.3: # %for.body
+; CHECK-NEXT:    #
+; CHECK-NEXT:    fabs 3, 2
+; CHECK-NEXT:    b .LBB0_5
+; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:    fnabs 3, 2
+; CHECK-NEXT:  .LBB0_5: # %for.body
+; CHECK-NEXT:    #
+; CHECK-NEXT:    fcmpu 0, 2, 3
+; CHECK-NEXT:    stfd 3, 56(1)
+; CHECK-NEXT:    beq 0, .LBB0_1
+; CHECK-NEXT:  # %bb.6: # %for.body
+; CHECK-NEXT:    #
+; CHECK-NEXT:    fneg 1, 1
+; CHECK-NEXT:    b .LBB0_1
+; CHECK-NEXT:  .LBB0_7: # %for.end
+; CHECK-NEXT:    stfd 2, 16(1)
 ; CHECK-NEXT:    lwz 3, 20(1)
-; CHECK-NEXT:    stfd 0, 8(1)
+; CHECK-NEXT:    stfd 1, 8(1)
 ; CHECK-NEXT:    stw 3, 36(1)
 ; CHECK-NEXT:    lwz 3, 16(1)
-; CHECK-NEXT:    lfd 31, 168(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    stw 3, 32(1)
 ; CHECK-NEXT:    lwz 3, 12(1)
 ; CHECK-NEXT:    lfd 1, 32(1)
 ; CHECK-NEXT:    stw 3, 28(1)
 ; CHECK-NEXT:    lwz 3, 8(1)
-; CHECK-NEXT:    lwz 30, 160(1) # 4-byte Folded Reload
 ; CHECK-NEXT:    stw 3, 24(1)
 ; CHECK-NEXT:    lfd 2, 24(1)
-; CHECK-NEXT:    lwz 0, 180(1)
-; CHECK-NEXT:    addi 1, 1, 176
-; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    addi 1, 1, 112
 ; CHECK-NEXT:    blr
 entry:
   br label %for.body
@@ -103,4 +100,3 @@ for.end:                                          ; preds = %for.body
 declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) #0
 
 ; CHECK-NOT: mtctr
-
diff --git a/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll b/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
