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[EarlyCSE] Regenerate test checks (NFC)
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-246
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8 files changed

+439
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‎llvm/test/Transforms/EarlyCSE/atomics.ll

Lines changed: 120 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -1,71 +1,86 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
12
; RUN: opt < %s -S -early-cse -earlycse-debug-hash | FileCheck %s
23
; RUN: opt < %s -S -basic-aa -early-cse-memssa | FileCheck %s
34

4-
; CHECK-LABEL: @test12(
55
define i32 @test12(i1 %B, i32* %P1, i32* %P2) {
6+
; CHECK-LABEL: @test12(
7+
; CHECK-NEXT: [[LOAD0:%.*]] = load i32, i32* [[P1:%.*]], align 4
8+
; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, i32* [[P2:%.*]] seq_cst, align 4
9+
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[P1]], align 4
10+
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[B:%.*]], i32 [[LOAD0]], i32 [[LOAD1]]
11+
; CHECK-NEXT: ret i32 [[SEL]]
12+
;
613
%load0 = load i32, i32* %P1
714
%1 = load atomic i32, i32* %P2 seq_cst, align 4
815
%load1 = load i32, i32* %P1
916
%sel = select i1 %B, i32 %load0, i32 %load1
1017
ret i32 %sel
11-
; CHECK: load i32, i32* %P1
12-
; CHECK: load i32, i32* %P1
1318
}
1419

15-
; CHECK-LABEL: @test13(
1620
; atomic to non-atomic forwarding is legal
1721
define i32 @test13(i1 %B, i32* %P1) {
22+
; CHECK-LABEL: @test13(
23+
; CHECK-NEXT: [[A:%.*]] = load atomic i32, i32* [[P1:%.*]] seq_cst, align 4
24+
; CHECK-NEXT: ret i32 0
25+
;
1826
%a = load atomic i32, i32* %P1 seq_cst, align 4
1927
%b = load i32, i32* %P1
2028
%res = sub i32 %a, %b
2129
ret i32 %res
22-
; CHECK: load atomic i32, i32* %P1
23-
; CHECK: ret i32 0
2430
}
2531

26-
; CHECK-LABEL: @test14(
2732
; atomic to unordered atomic forwarding is legal
2833
define i32 @test14(i1 %B, i32* %P1) {
34+
; CHECK-LABEL: @test14(
35+
; CHECK-NEXT: [[A:%.*]] = load atomic i32, i32* [[P1:%.*]] seq_cst, align 4
36+
; CHECK-NEXT: ret i32 0
37+
;
2938
%a = load atomic i32, i32* %P1 seq_cst, align 4
3039
%b = load atomic i32, i32* %P1 unordered, align 4
3140
%res = sub i32 %a, %b
3241
ret i32 %res
33-
; CHECK: load atomic i32, i32* %P1 seq_cst
34-
; CHECK-NEXT: ret i32 0
3542
}
3643

37-
; CHECK-LABEL: @test15(
3844
; implementation restriction: can't forward to stonger
3945
; than unordered
4046
define i32 @test15(i1 %B, i32* %P1, i32* %P2) {
47+
; CHECK-LABEL: @test15(
48+
; CHECK-NEXT: [[A:%.*]] = load atomic i32, i32* [[P1:%.*]] seq_cst, align 4
49+
; CHECK-NEXT: [[B:%.*]] = load atomic i32, i32* [[P1]] seq_cst, align 4
50+
; CHECK-NEXT: [[RES:%.*]] = sub i32 [[A]], [[B]]
51+
; CHECK-NEXT: ret i32 [[RES]]
52+
;
4153
%a = load atomic i32, i32* %P1 seq_cst, align 4
4254
%b = load atomic i32, i32* %P1 seq_cst, align 4
4355
%res = sub i32 %a, %b
4456
ret i32 %res
45-
; CHECK: load atomic i32, i32* %P1
46-
; CHECK: load atomic i32, i32* %P1
4757
}
4858

49-
; CHECK-LABEL: @test16(
5059
; forwarding non-atomic to atomic is wrong! (However,
5160
; it would be legal to use the later value in place of the
5261
; former in this particular example. We just don't
5362
; do that right now.)
5463
define i32 @test16(i1 %B, i32* %P1, i32* %P2) {
64+
; CHECK-LABEL: @test16(
65+
; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[P1:%.*]], align 4
66+
; CHECK-NEXT: [[B:%.*]] = load atomic i32, i32* [[P1]] unordered, align 4
67+
; CHECK-NEXT: [[RES:%.*]] = sub i32 [[A]], [[B]]
68+
; CHECK-NEXT: ret i32 [[RES]]
69+
;
5570
%a = load i32, i32* %P1, align 4
5671
%b = load atomic i32, i32* %P1 unordered, align 4
5772
%res = sub i32 %a, %b
5873
ret i32 %res
59-
; CHECK: load i32, i32* %P1
60-
; CHECK: load atomic i32, i32* %P1
6174
}
6275

6376
; Can't DSE across a full fence
6477
define void @fence_seq_cst_store(i1 %B, i32* %P1, i32* %P2) {
65-
; CHECK-LABEL: @fence_seq_cst_store
66-
; CHECK: store
67-
; CHECK: store atomic
68-
; CHECK: store
78+
; CHECK-LABEL: @fence_seq_cst_store(
79+
; CHECK-NEXT: store i32 0, i32* [[P1:%.*]], align 4
80+
; CHECK-NEXT: store atomic i32 0, i32* [[P2:%.*]] seq_cst, align 4
81+
; CHECK-NEXT: store i32 0, i32* [[P1]], align 4
82+
; CHECK-NEXT: ret void
83+
;
6984
store i32 0, i32* %P1, align 4
7085
store atomic i32 0, i32* %P2 seq_cst, align 4
7186
store i32 0, i32* %P1, align 4
@@ -74,10 +89,12 @@ define void @fence_seq_cst_store(i1 %B, i32* %P1, i32* %P2) {
7489

7590
; Can't DSE across a full fence
7691
define void @fence_seq_cst(i1 %B, i32* %P1, i32* %P2) {
77-
; CHECK-LABEL: @fence_seq_cst
78-
; CHECK: store
79-
; CHECK: fence seq_cst
80-
; CHECK: store
92+
; CHECK-LABEL: @fence_seq_cst(
93+
; CHECK-NEXT: store i32 0, i32* [[P1:%.*]], align 4
94+
; CHECK-NEXT: fence seq_cst
95+
; CHECK-NEXT: store i32 0, i32* [[P1]], align 4
96+
; CHECK-NEXT: ret void
97+
;
8198
store i32 0, i32* %P1, align 4
8299
fence seq_cst
83100
store i32 0, i32* %P1, align 4
@@ -86,10 +103,12 @@ define void @fence_seq_cst(i1 %B, i32* %P1, i32* %P2) {
86103

87104
; Can't DSE across a full fence
88105
define void @fence_asm_sideeffect(i1 %B, i32* %P1, i32* %P2) {
89-
; CHECK-LABEL: @fence_asm_sideeffect
90-
; CHECK: store
91-
; CHECK: call void asm sideeffect
92-
; CHECK: store
106+
; CHECK-LABEL: @fence_asm_sideeffect(
107+
; CHECK-NEXT: store i32 0, i32* [[P1:%.*]], align 4
108+
; CHECK-NEXT: call void asm sideeffect "", ""()
109+
; CHECK-NEXT: store i32 0, i32* [[P1]], align 4
110+
; CHECK-NEXT: ret void
111+
;
93112
store i32 0, i32* %P1, align 4
94113
call void asm sideeffect "", ""()
95114
store i32 0, i32* %P1, align 4
@@ -98,10 +117,12 @@ define void @fence_asm_sideeffect(i1 %B, i32* %P1, i32* %P2) {
98117

99118
; Can't DSE across a full fence
100119
define void @fence_asm_memory(i1 %B, i32* %P1, i32* %P2) {
101-
; CHECK-LABEL: @fence_asm_memory
102-
; CHECK: store
103-
; CHECK: call void asm
104-
; CHECK: store
120+
; CHECK-LABEL: @fence_asm_memory(
121+
; CHECK-NEXT: store i32 0, i32* [[P1:%.*]], align 4
122+
; CHECK-NEXT: call void asm "", "~{memory}"()
123+
; CHECK-NEXT: store i32 0, i32* [[P1]], align 4
124+
; CHECK-NEXT: ret void
125+
;
105126
store i32 0, i32* %P1, align 4
106127
call void asm "", "~{memory}"()
107128
store i32 0, i32* %P1, align 4
@@ -110,82 +131,98 @@ define void @fence_asm_memory(i1 %B, i32* %P1, i32* %P2) {
110131

111132
; Can't remove a volatile load
112133
define i32 @volatile_load(i1 %B, i32* %P1, i32* %P2) {
134+
; CHECK-LABEL: @volatile_load(
135+
; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[P1:%.*]], align 4
136+
; CHECK-NEXT: [[B:%.*]] = load volatile i32, i32* [[P1]], align 4
137+
; CHECK-NEXT: [[RES:%.*]] = sub i32 [[A]], [[B]]
138+
; CHECK-NEXT: ret i32 [[RES]]
139+
;
113140
%a = load i32, i32* %P1, align 4
114141
%b = load volatile i32, i32* %P1, align 4
115142
%res = sub i32 %a, %b
116143
ret i32 %res
117-
; CHECK-LABEL: @volatile_load
118-
; CHECK: load i32, i32* %P1
119-
; CHECK: load volatile i32, i32* %P1
120144
}
121145

122146
; Can't remove redundant volatile loads
123147
define i32 @redundant_volatile_load(i1 %B, i32* %P1, i32* %P2) {
148+
; CHECK-LABEL: @redundant_volatile_load(
149+
; CHECK-NEXT: [[A:%.*]] = load volatile i32, i32* [[P1:%.*]], align 4
150+
; CHECK-NEXT: [[B:%.*]] = load volatile i32, i32* [[P1]], align 4
151+
; CHECK-NEXT: [[RES:%.*]] = sub i32 [[A]], [[B]]
152+
; CHECK-NEXT: ret i32 [[RES]]
153+
;
124154
%a = load volatile i32, i32* %P1, align 4
125155
%b = load volatile i32, i32* %P1, align 4
126156
%res = sub i32 %a, %b
127157
ret i32 %res
128-
; CHECK-LABEL: @redundant_volatile_load
129-
; CHECK: load volatile i32, i32* %P1
130-
; CHECK: load volatile i32, i32* %P1
131-
; CHECK: sub
132158
}
133159

134160
; Can't DSE a volatile store
135161
define void @volatile_store(i1 %B, i32* %P1, i32* %P2) {
136-
; CHECK-LABEL: @volatile_store
137-
; CHECK: store volatile
138-
; CHECK: store
162+
; CHECK-LABEL: @volatile_store(
163+
; CHECK-NEXT: store volatile i32 0, i32* [[P1:%.*]], align 4
164+
; CHECK-NEXT: store i32 3, i32* [[P1]], align 4
165+
; CHECK-NEXT: ret void
166+
;
139167
store volatile i32 0, i32* %P1, align 4
140168
store i32 3, i32* %P1, align 4
141169
ret void
142170
}
143171

144172
; Can't DSE a redundant volatile store
145173
define void @redundant_volatile_store(i1 %B, i32* %P1, i32* %P2) {
146-
; CHECK-LABEL: @redundant_volatile_store
147-
; CHECK: store volatile
148-
; CHECK: store volatile
174+
; CHECK-LABEL: @redundant_volatile_store(
175+
; CHECK-NEXT: store volatile i32 0, i32* [[P1:%.*]], align 4
176+
; CHECK-NEXT: store volatile i32 0, i32* [[P1]], align 4
177+
; CHECK-NEXT: ret void
178+
;
149179
store volatile i32 0, i32* %P1, align 4
150180
store volatile i32 0, i32* %P1, align 4
151181
ret void
152182
}
153183

154184
; Can value forward from volatiles
155185
define i32 @test20(i1 %B, i32* %P1, i32* %P2) {
186+
; CHECK-LABEL: @test20(
187+
; CHECK-NEXT: [[A:%.*]] = load volatile i32, i32* [[P1:%.*]], align 4
188+
; CHECK-NEXT: ret i32 0
189+
;
156190
%a = load volatile i32, i32* %P1, align 4
157191
%b = load i32, i32* %P1, align 4
158192
%res = sub i32 %a, %b
159193
ret i32 %res
160-
; CHECK-LABEL: @test20
161-
; CHECK: load volatile i32, i32* %P1
162-
; CHECK: ret i32 0
163194
}
164195

165196
; Can DSE a non-volatile store in favor of a volatile one
166197
; currently a missed optimization
167198
define void @test21(i1 %B, i32* %P1, i32* %P2) {
168-
; CHECK-LABEL: @test21
169-
; CHECK: store
170-
; CHECK: store volatile
199+
; CHECK-LABEL: @test21(
200+
; CHECK-NEXT: store i32 0, i32* [[P1:%.*]], align 4
201+
; CHECK-NEXT: store volatile i32 3, i32* [[P1]], align 4
202+
; CHECK-NEXT: ret void
203+
;
171204
store i32 0, i32* %P1, align 4
172205
store volatile i32 3, i32* %P1, align 4
173206
ret void
174207
}
175208

176209
; Can DSE a normal store in favor of a unordered one
177210
define void @test22(i1 %B, i32* %P1, i32* %P2) {
178-
; CHECK-LABEL: @test22
179-
; CHECK-NEXT: store atomic
211+
; CHECK-LABEL: @test22(
212+
; CHECK-NEXT: store atomic i32 3, i32* [[P1:%.*]] unordered, align 4
213+
; CHECK-NEXT: ret void
214+
;
180215
store i32 0, i32* %P1, align 4
181216
store atomic i32 3, i32* %P1 unordered, align 4
182217
ret void
183218
}
184219

185220
; Can also DSE a unordered store in favor of a normal one
186221
define void @test23(i1 %B, i32* %P1, i32* %P2) {
187-
; CHECK-LABEL: @test23
188-
; CHECK-NEXT: store i32 0
222+
; CHECK-LABEL: @test23(
223+
; CHECK-NEXT: store i32 0, i32* [[P1:%.*]], align 4
224+
; CHECK-NEXT: ret void
225+
;
189226
store atomic i32 3, i32* %P1 unordered, align 4
190227
store i32 0, i32* %P1, align 4
191228
ret void
@@ -195,9 +232,11 @@ define void @test23(i1 %B, i32* %P1, i32* %P2) {
195232
; Note that we could remove the earlier store if we could
196233
; represent the required ordering.
197234
define void @test24(i1 %B, i32* %P1, i32* %P2) {
198-
; CHECK-LABEL: @test24
199-
; CHECK-NEXT: store atomic
200-
; CHECK-NEXT: store i32 0
235+
; CHECK-LABEL: @test24(
236+
; CHECK-NEXT: store atomic i32 3, i32* [[P1:%.*]] release, align 4
237+
; CHECK-NEXT: store i32 0, i32* [[P1]], align 4
238+
; CHECK-NEXT: ret void
239+
;
201240
store atomic i32 3, i32* %P1 release, align 4
202241
store i32 0, i32* %P1, align 4
203242
ret void
@@ -206,19 +245,22 @@ define void @test24(i1 %B, i32* %P1, i32* %P2) {
206245
; Can't remove volatile stores - each is independently observable and
207246
; the count of such stores is an observable program side effect.
208247
define void @test25(i1 %B, i32* %P1, i32* %P2) {
209-
; CHECK-LABEL: @test25
210-
; CHECK-NEXT: store volatile
211-
; CHECK-NEXT: store volatile
248+
; CHECK-LABEL: @test25(
249+
; CHECK-NEXT: store volatile i32 3, i32* [[P1:%.*]], align 4
250+
; CHECK-NEXT: store volatile i32 0, i32* [[P1]], align 4
251+
; CHECK-NEXT: ret void
252+
;
212253
store volatile i32 3, i32* %P1, align 4
213254
store volatile i32 0, i32* %P1, align 4
214255
ret void
215256
}
216257

217258
; Can DSE a unordered store in favor of a unordered one
218259
define void @test26(i1 %B, i32* %P1, i32* %P2) {
219-
; CHECK-LABEL: @test26
220-
; CHECK-NEXT: store atomic i32 3, i32* %P1 unordered, align 4
221-
; CHECK-NEXT: ret
260+
; CHECK-LABEL: @test26(
261+
; CHECK-NEXT: store atomic i32 3, i32* [[P1:%.*]] unordered, align 4
262+
; CHECK-NEXT: ret void
263+
;
222264
store atomic i32 0, i32* %P1 unordered, align 4
223265
store atomic i32 3, i32* %P1 unordered, align 4
224266
ret void
@@ -227,10 +269,11 @@ define void @test26(i1 %B, i32* %P1, i32* %P2) {
227269
; Can DSE a unordered store in favor of a ordered one,
228270
; but current don't due to implementation limits
229271
define void @test27(i1 %B, i32* %P1, i32* %P2) {
230-
; CHECK-LABEL: @test27
231-
; CHECK-NEXT: store atomic i32 0, i32* %P1 unordered, align 4
232-
; CHECK-NEXT: store atomic i32 3, i32* %P1 release, align 4
233-
; CHECK-NEXT: ret
272+
; CHECK-LABEL: @test27(
273+
; CHECK-NEXT: store atomic i32 0, i32* [[P1:%.*]] unordered, align 4
274+
; CHECK-NEXT: store atomic i32 3, i32* [[P1]] release, align 4
275+
; CHECK-NEXT: ret void
276+
;
234277
store atomic i32 0, i32* %P1 unordered, align 4
235278
store atomic i32 3, i32* %P1 release, align 4
236279
ret void
@@ -239,10 +282,11 @@ define void @test27(i1 %B, i32* %P1, i32* %P2) {
239282
; Can DSE an unordered atomic store in favor of an
240283
; ordered one, but current don't due to implementation limits
241284
define void @test28(i1 %B, i32* %P1, i32* %P2) {
242-
; CHECK-LABEL: @test28
243-
; CHECK-NEXT: store atomic i32 0, i32* %P1 unordered, align 4
244-
; CHECK-NEXT: store atomic i32 3, i32* %P1 release, align 4
245-
; CHECK-NEXT: ret
285+
; CHECK-LABEL: @test28(
286+
; CHECK-NEXT: store atomic i32 0, i32* [[P1:%.*]] unordered, align 4
287+
; CHECK-NEXT: store atomic i32 3, i32* [[P1]] release, align 4
288+
; CHECK-NEXT: ret void
289+
;
246290
store atomic i32 0, i32* %P1 unordered, align 4
247291
store atomic i32 3, i32* %P1 release, align 4
248292
ret void
@@ -251,9 +295,11 @@ define void @test28(i1 %B, i32* %P1, i32* %P2) {
251295
; As an implementation limitation, can't remove ordered stores
252296
; see also: @test24
253297
define void @test29(i1 %B, i32* %P1, i32* %P2) {
254-
; CHECK-LABEL: @test29
255-
; CHECK-NEXT: store atomic
256-
; CHECK-NEXT: store atomic
298+
; CHECK-LABEL: @test29(
299+
; CHECK-NEXT: store atomic i32 3, i32* [[P1:%.*]] release, align 4
300+
; CHECK-NEXT: store atomic i32 0, i32* [[P1]] unordered, align 4
301+
; CHECK-NEXT: ret void
302+
;
257303
store atomic i32 3, i32* %P1 release, align 4
258304
store atomic i32 0, i32* %P1 unordered, align 4
259305
ret void

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