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‎llvm/test/CodeGen/AArch64/no-sink-vector-cmp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <4 x i32> @no_sink_simple(<4 x i32> %a, <4 x i32> %b, i1 %c, ptr %p) {
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; CHECK-LABEL: no_sink_simple:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tbz w0, #0, .LBB0_2
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; CHECK-NEXT: // %bb.1: // %s
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; CHECK-NEXT: cmgt v1.4s, v1.4s, v0.4s
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_2: // %t
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; CHECK-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%d = icmp slt <4 x i32> %a, %b
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br i1 %c, label %s, label %t
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s:
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%s1 = select <4 x i1> %d, <4 x i32> %a, <4 x i32> zeroinitializer
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store <4 x i32> %s1, ptr %p
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ret <4 x i32> %s1
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t:
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%s2 = select <4 x i1> %d, <4 x i32> %b, <4 x i32> zeroinitializer
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ret <4 x i32> %s2
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}
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define void @vector_loop_with_icmp(ptr nocapture noundef writeonly %dest) {
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; CHECK-LABEL: vector_loop_with_icmp:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #15 // =0xf
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; CHECK-NEXT: mov w10, #4 // =0x4
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; CHECK-NEXT: adrp x9, .LCPI1_0
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; CHECK-NEXT: adrp x11, .LCPI1_1
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; CHECK-NEXT: dup v0.2d, x8
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; CHECK-NEXT: dup v1.2d, x10
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; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI1_0]
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; CHECK-NEXT: ldr q3, [x11, :lo12:.LCPI1_1]
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; CHECK-NEXT: add x9, x0, #8
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; CHECK-NEXT: mov w10, #16 // =0x10
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; CHECK-NEXT: mov w11, #1 // =0x1
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; CHECK-NEXT: b .LBB1_2
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; CHECK-NEXT: .LBB1_1: // %pred.store.continue18
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: add v2.2d, v2.2d, v1.2d
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; CHECK-NEXT: add v3.2d, v3.2d, v1.2d
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; CHECK-NEXT: subs x10, x10, #4
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; CHECK-NEXT: add x9, x9, #16
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; CHECK-NEXT: b.eq .LBB1_10
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; CHECK-NEXT: .LBB1_2: // %vector.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmhi v4.2d, v0.2d, v3.2d
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; CHECK-NEXT: xtn v4.2s, v4.2d
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; CHECK-NEXT: uzp1 v4.4h, v4.4h, v0.4h
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; CHECK-NEXT: umov w12, v4.h[0]
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; CHECK-NEXT: tbz w12, #0, .LBB1_4
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; CHECK-NEXT: // %bb.3: // %pred.store.if
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: stur w11, [x9, #-8]
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; CHECK-NEXT: .LBB1_4: // %pred.store.continue
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: dup v4.2d, x8
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; CHECK-NEXT: cmhi v4.2d, v4.2d, v3.2d
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; CHECK-NEXT: xtn v4.2s, v4.2d
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; CHECK-NEXT: uzp1 v4.4h, v4.4h, v0.4h
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; CHECK-NEXT: umov w12, v4.h[1]
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; CHECK-NEXT: tbz w12, #0, .LBB1_6
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; CHECK-NEXT: // %bb.5: // %pred.store.if5
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: stur w11, [x9, #-4]
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; CHECK-NEXT: .LBB1_6: // %pred.store.continue6
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: dup v4.2d, x8
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; CHECK-NEXT: cmhi v4.2d, v4.2d, v2.2d
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; CHECK-NEXT: xtn v4.2s, v4.2d
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; CHECK-NEXT: uzp1 v4.4h, v0.4h, v4.4h
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; CHECK-NEXT: umov w12, v4.h[2]
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; CHECK-NEXT: tbz w12, #0, .LBB1_8
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; CHECK-NEXT: // %bb.7: // %pred.store.if7
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: str w11, [x9]
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; CHECK-NEXT: .LBB1_8: // %pred.store.continue8
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: dup v4.2d, x8
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; CHECK-NEXT: cmhi v4.2d, v4.2d, v2.2d
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; CHECK-NEXT: xtn v4.2s, v4.2d
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; CHECK-NEXT: uzp1 v4.4h, v0.4h, v4.4h
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; CHECK-NEXT: umov w12, v4.h[3]
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; CHECK-NEXT: tbz w12, #0, .LBB1_1
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; CHECK-NEXT: // %bb.9: // %pred.store.if9
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: str w11, [x9, #4]
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; CHECK-NEXT: b .LBB1_1
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; CHECK-NEXT: .LBB1_10: // %for.cond.cleanup
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; CHECK-NEXT: ret
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entry:
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next, %pred.store.continue18 ]
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%vec.ind = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %entry ], [ %vec.ind.next, %pred.store.continue18 ]
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%0 = icmp ult <4 x i64> %vec.ind, <i64 15, i64 15, i64 15, i64 15>
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%1 = extractelement <4 x i1> %0, i64 0
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br i1 %1, label %pred.store.if, label %pred.store.continue
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pred.store.if:
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%2 = getelementptr inbounds i32, ptr %dest, i64 %index
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store i32 1, ptr %2, align 4
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br label %pred.store.continue
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pred.store.continue:
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%3 = extractelement <4 x i1> %0, i64 1
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br i1 %3, label %pred.store.if5, label %pred.store.continue6
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pred.store.if5:
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%4 = or disjoint i64 %index, 1
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%5 = getelementptr inbounds i32, ptr %dest, i64 %4
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store i32 1, ptr %5, align 4
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br label %pred.store.continue6
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pred.store.continue6:
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%6 = extractelement <4 x i1> %0, i64 2
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br i1 %6, label %pred.store.if7, label %pred.store.continue8
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pred.store.if7:
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%7 = or disjoint i64 %index, 2
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%8 = getelementptr inbounds i32, ptr %dest, i64 %7
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store i32 1, ptr %8, align 4
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br label %pred.store.continue8
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pred.store.continue8:
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%9 = extractelement <4 x i1> %0, i64 3
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br i1 %9, label %pred.store.if9, label %pred.store.continue18
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pred.store.if9:
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%10 = or disjoint i64 %index, 3
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%11 = getelementptr inbounds i32, ptr %dest, i64 %10
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store i32 1, ptr %11, align 4
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br label %pred.store.continue18
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pred.store.continue18:
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%index.next = add i64 %index, 4
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%vec.ind.next = add <4 x i64> %vec.ind, <i64 4, i64 4, i64 4, i64 4>
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%24 = icmp eq i64 %index.next, 16
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br i1 %24, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup:
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ret void
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}

‎llvm/test/CodeGen/Thumb2/mve-sink-vector-cmp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve < %s | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @no_sink_simple(<4 x i32> %a, <4 x i32> %b, i1 %c, ptr %p) {
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; CHECK-LABEL: no_sink_simple:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsls r0, r0, #31
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; CHECK-NEXT: beq .LBB0_2
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; CHECK-NEXT: @ %bb.1: @ %s
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; CHECK-NEXT: vcmp.s32 gt, q1, q0
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: vstrw.32 q0, [r1]
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .LBB0_2: @ %t
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; CHECK-NEXT: vcmp.s32 gt, q1, q0
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; CHECK-NEXT: vmov.i32 q0, #0x0
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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%d = icmp slt <4 x i32> %a, %b
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br i1 %c, label %s, label %t
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s:
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%s1 = select <4 x i1> %d, <4 x i32> %a, <4 x i32> zeroinitializer
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store <4 x i32> %s1, ptr %p
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ret <4 x i32> %s1
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t:
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%s2 = select <4 x i1> %d, <4 x i32> %b, <4 x i32> zeroinitializer
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ret <4 x i32> %s2
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}
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define arm_aapcs_vfpcc void @vector_loop_with_icmp(ptr nocapture noundef writeonly %dest) {
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; CHECK-LABEL: vector_loop_with_icmp:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: adr r1, .LCPI1_0
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; CHECK-NEXT: vmov.i32 q1, #0xf
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; CHECK-NEXT: vldrw.u32 q0, [r1]
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; CHECK-NEXT: movs r1, #0
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; CHECK-NEXT: mov.w lr, #1
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; CHECK-NEXT: vmov.i32 q2, #0xf
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; CHECK-NEXT: vmov.i32 q3, #0xf
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; CHECK-NEXT: vmov.i32 q4, #0xf
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; CHECK-NEXT: mov.w r12, #4
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: .LBB1_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vcmp.u32 hi, q1, q0
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; CHECK-NEXT: vmrs r2, p0
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; CHECK-NEXT: vcmp.u32 hi, q2, q0
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; CHECK-NEXT: lsls r2, r2, #31
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; CHECK-NEXT: it ne
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; CHECK-NEXT: strne.w lr, [r0, r1, lsl #2]
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; CHECK-NEXT: vmrs r2, p0
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; CHECK-NEXT: vcmp.u32 hi, q3, q0
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; CHECK-NEXT: lsrs r2, r2, #4
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; CHECK-NEXT: lsls r2, r2, #31
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; CHECK-NEXT: itt ne
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; CHECK-NEXT: orrne r2, r1, #1
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; CHECK-NEXT: strne.w lr, [r0, r2, lsl #2]
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; CHECK-NEXT: vmrs r2, p0
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; CHECK-NEXT: vcmp.u32 hi, q4, q0
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; CHECK-NEXT: vadd.i32 q0, q0, r12
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; CHECK-NEXT: lsrs r2, r2, #8
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; CHECK-NEXT: lsls r2, r2, #31
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; CHECK-NEXT: itt ne
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; CHECK-NEXT: orrne r2, r1, #2
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; CHECK-NEXT: strne.w lr, [r0, r2, lsl #2]
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; CHECK-NEXT: vmrs r2, p0
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; CHECK-NEXT: lsrs r2, r2, #12
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; CHECK-NEXT: lsls r2, r2, #31
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; CHECK-NEXT: itt ne
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; CHECK-NEXT: orrne r2, r1, #3
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; CHECK-NEXT: strne.w lr, [r0, r2, lsl #2]
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; CHECK-NEXT: adds r1, #4
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; CHECK-NEXT: adc r3, r3, #0
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; CHECK-NEXT: eor r2, r1, #16
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; CHECK-NEXT: orrs r2, r3
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; CHECK-NEXT: bne .LBB1_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.3:
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; CHECK-NEXT: .LCPI1_0:
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 2 @ 0x2
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; CHECK-NEXT: .long 3 @ 0x3
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entry:
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next, %pred.store.continue18 ]
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%vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %entry ], [ %vec.ind.next, %pred.store.continue18 ]
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%0 = icmp ult <4 x i32> %vec.ind, <i32 15, i32 15, i32 15, i32 15>
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%1 = extractelement <4 x i1> %0, i64 0
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br i1 %1, label %pred.store.if, label %pred.store.continue
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pred.store.if:
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%2 = getelementptr inbounds i32, ptr %dest, i64 %index
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store i32 1, ptr %2, align 4
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br label %pred.store.continue
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pred.store.continue:
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%3 = extractelement <4 x i1> %0, i64 1
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br i1 %3, label %pred.store.if5, label %pred.store.continue6
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pred.store.if5:
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%4 = or disjoint i64 %index, 1
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%5 = getelementptr inbounds i32, ptr %dest, i64 %4
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store i32 1, ptr %5, align 4
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br label %pred.store.continue6
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pred.store.continue6:
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%6 = extractelement <4 x i1> %0, i64 2
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br i1 %6, label %pred.store.if7, label %pred.store.continue8
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pred.store.if7:
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%7 = or disjoint i64 %index, 2
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%8 = getelementptr inbounds i32, ptr %dest, i64 %7
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store i32 1, ptr %8, align 4
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br label %pred.store.continue8
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pred.store.continue8:
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%9 = extractelement <4 x i1> %0, i64 3
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br i1 %9, label %pred.store.if9, label %pred.store.continue18
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pred.store.if9:
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%10 = or disjoint i64 %index, 3
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%11 = getelementptr inbounds i32, ptr %dest, i64 %10
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store i32 1, ptr %11, align 4
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br label %pred.store.continue18
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pred.store.continue18:
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%index.next = add i64 %index, 4
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%vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>
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%24 = icmp eq i64 %index.next, 16
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br i1 %24, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup:
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ret void
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}

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