test ci 2

Author: Thorsten Schütt

llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir

@@ -1,4 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SELECT
 # RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=regbankselect %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-REGBANK
 # RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -run-pass=legalizer  %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LEGAL
 
@@ -8,6 +9,11 @@
 name:            test_splat_vector_s64
 body:             |
   bb.1:
+    ; CHECK-SELECT-LABEL: name: test_splat_vector_s64
+    ; CHECK-SELECT: %imm:gpr64sp = COPY $x0
+    ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D %imm
+    ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+    ;
     ; CHECK-REGBANK-LABEL: name: test_splat_vector_s64
     ; CHECK-REGBANK: %imm:gpr(s64) = COPY $x0
     ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
@@ -25,6 +31,12 @@ body:             |
 name:            test_splat_vector_s64_const
 body:             |
   bb.1:
+    ; CHECK-SELECT-LABEL: name: test_splat_vector_s64_const
+    ; CHECK-SELECT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 9
+    ; CHECK-SELECT-NEXT: %imm:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
+    ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D %imm
+    ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+    ;
     ; CHECK-REGBANK-LABEL: name: test_splat_vector_s64_const
     ; CHECK-REGBANK: %imm:gpr(s64) = G_CONSTANT i64 9
     ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
@@ -42,6 +54,12 @@ body:             |
 name:            test_splat_vector_s64_fconst
 body:             |
   bb.1:
+    ; CHECK-SELECT-LABEL: name: test_splat_vector_s64_fconst
+    ; CHECK-SELECT: %imm:fpr64 = FMOVDi 34
+    ; CHECK-SELECT-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY %imm
+    ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D [[COPY]]
+    ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+    ;
     ; CHECK-REGBANK-LABEL: name: test_splat_vector_s64_fconst
     ; CHECK-REGBANK: %imm:fpr(s64) = G_FCONSTANT double 9.000000e+00
     ; CHECK-REGBANK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY %imm(s64)
@@ -60,6 +78,11 @@ body:             |
 name:            test_splat_vector_s32
 body:             |
   bb.1:
+    ; CHECK-SELECT-LABEL: name: test_splat_vector_s32
+    ; CHECK-SELECT: %imm:gpr32sp = COPY $w0
+    ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S %imm
+    ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+    ;
     ; CHECK-REGBANK-LABEL: name: test_splat_vector_s32
     ; CHECK-REGBANK: %imm:gpr(s32) = COPY $w0
     ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
@@ -77,6 +100,11 @@ body:             |
 name:            test_splat_vector_s32_const
 body:             |
   bb.1:
+    ; CHECK-SELECT-LABEL: name: test_splat_vector_s32_const
+    ; CHECK-SELECT: %imm:gpr32common = MOVi32imm 9
+    ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S %imm
+    ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+    ;
     ; CHECK-REGBANK-LABEL: name: test_splat_vector_s32_const
     ; CHECK-REGBANK: %imm:gpr(s32) = G_CONSTANT i32 9
     ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
@@ -94,6 +122,12 @@ body:             |
 name:            test_splat_vector_s32_fconst
 body:             |
   bb.1:
+    ; CHECK-SELECT-LABEL: name: test_splat_vector_s32_fconst
+    ; CHECK-SELECT: %imm:fpr32 = FMOVSi 28
+    ; CHECK-SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY %imm
+    ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S [[COPY]]
+    ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+    ;
     ; CHECK-REGBANK-LABEL: name: test_splat_vector_s32_fconst
     ; CHECK-REGBANK: %imm:fpr(s32) = G_FCONSTANT float 7.000000e+00
     ; CHECK-REGBANK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %imm(s32)