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jayfoadjayfoad
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[AMDGPU] Only try DecoderTables for the current subtarget. NFCI. (#82992)
Speed up disassembly by only calling tryDecodeInst for DecoderTables that make sense for the current subtarget. This gives a 1.3x speed-up on check-llvm-mc-disassembler-amdgpu in my Release+Asserts build.
1 parent a35599b commit 60e7ae3

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3 files changed

+34
-18
lines changed

3 files changed

+34
-18
lines changed

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 30 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -466,15 +466,18 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
466466
if (isGFX11Plus() && Bytes.size() >= 12 ) {
467467
DecoderUInt128 DecW = eat12Bytes(Bytes);
468468

469-
if (tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI,
469+
if (isGFX11() &&
470+
tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI,
470471
DecW, Address, CS))
471472
break;
472473

473-
if (tryDecodeInst(DecoderTableGFX1296, DecoderTableGFX12_FAKE1696, MI,
474+
if (isGFX12() &&
475+
tryDecodeInst(DecoderTableGFX1296, DecoderTableGFX12_FAKE1696, MI,
474476
DecW, Address, CS))
475477
break;
476478

477-
if (tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS))
479+
if (isGFX12() &&
480+
tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS))
478481
break;
479482
}
480483

@@ -507,27 +510,32 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
507510
tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS))
508511
break;
509512

510-
if (tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS))
513+
if ((isVI() || isGFX9()) &&
514+
tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS))
511515
break;
512516

513-
if (tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS))
517+
if (isGFX9() && tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS))
514518
break;
515519

516-
if (tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS))
520+
if (isGFX10() && tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS))
517521
break;
518522

519-
if (tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW,
523+
if (isGFX12() &&
524+
tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW,
520525
Address, CS))
521526
break;
522527

523-
if (tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW,
528+
if (isGFX11() &&
529+
tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW,
524530
Address, CS))
525531
break;
526532

527-
if (tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS))
533+
if (isGFX11() &&
534+
tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS))
528535
break;
529536

530-
if (tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS))
537+
if (isGFX12() &&
538+
tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS))
531539
break;
532540
}
533541

@@ -538,13 +546,14 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
538546
if (Bytes.size() >= 4) {
539547
const uint32_t DW = eatBytes<uint32_t>(Bytes);
540548

541-
if (tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS))
549+
if ((isVI() || isGFX9()) &&
550+
tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS))
542551
break;
543552

544553
if (tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS))
545554
break;
546555

547-
if (tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS))
556+
if (isGFX9() && tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS))
548557
break;
549558

550559
if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) &&
@@ -555,14 +564,16 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
555564
tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS))
556565
break;
557566

558-
if (tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS))
567+
if (isGFX10() && tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS))
559568
break;
560569

561-
if (tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW,
570+
if (isGFX11() &&
571+
tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW,
562572
Address, CS))
563573
break;
564574

565-
if (tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW,
575+
if (isGFX12() &&
576+
tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW,
566577
Address, CS))
567578
break;
568579
}
@@ -1750,6 +1761,10 @@ bool AMDGPUDisassembler::isGFX11Plus() const {
17501761
return AMDGPU::isGFX11Plus(STI);
17511762
}
17521763

1764+
bool AMDGPUDisassembler::isGFX12() const {
1765+
return STI.hasFeature(AMDGPU::FeatureGFX12);
1766+
}
1767+
17531768
bool AMDGPUDisassembler::isGFX12Plus() const {
17541769
return AMDGPU::isGFX12Plus(STI);
17551770
}

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -275,6 +275,7 @@ class AMDGPUDisassembler : public MCDisassembler {
275275
bool isGFX10Plus() const;
276276
bool isGFX11() const;
277277
bool isGFX11Plus() const;
278+
bool isGFX12() const;
278279
bool isGFX12Plus() const;
279280

280281
bool hasArchitectedFlatScratch() const;

‎llvm/lib/Target/AMDGPU/MIMGInstructions.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -527,7 +527,7 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
527527
let ssamp = 0 in {
528528
if op.HAS_GFX10M then {
529529
def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
530-
!if(enableDisasm, "GFX10", "")>;
530+
!if(enableDisasm, "GFX8", "")>;
531531
if !not(ExtendedImageInst) then
532532
def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32,
533533
!if(enableDisasm, "GFX90A", "")>;
@@ -754,7 +754,7 @@ multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
754754
let ssamp = 0 in {
755755
if op.HAS_GFX10M then {
756756
def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32,
757-
!if(enableDisasm, "GFX10", "")>;
757+
!if(enableDisasm, "GFX8", "")>;
758758
let hasPostISelHook = 1 in
759759
def _V1_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VGPR_32,
760760
!if(enableDisasm, "GFX90A", "")>;
@@ -1298,7 +1298,7 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
12981298
if op.HAS_GFX10M then {
12991299
def _V # addr.NumWords
13001300
: MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass,
1301-
!if(!and(enableDisasm, addr.Disassemble), "GFX10", "")>;
1301+
!if(!and(enableDisasm, addr.Disassemble), "GFX8", "")>;
13021302
if !not(ExtendedImageInst) then
13031303
def _V # addr.NumWords # _gfx90a
13041304
: MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass,

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