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[RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (#93735)
According to our performance measurements, FLH/W/D have load latencies closer to 5 rather than 6 in these two models.
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4 files changed

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lines changed

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -140,7 +140,7 @@ def : WriteRes<WriteLDW, [SiFiveP400Load]>;
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def : WriteRes<WriteLDD, [SiFiveP400Load]>;
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}
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let Latency = 6 in {
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let Latency = 5 in {
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def : WriteRes<WriteFLD16, [SiFiveP400Load]>;
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def : WriteRes<WriteFLD32, [SiFiveP400Load]>;
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def : WriteRes<WriteFLD64, [SiFiveP400Load]>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,7 @@ def : WriteRes<WriteLDW, [SiFiveP600LDST]>;
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def : WriteRes<WriteLDD, [SiFiveP600LDST]>;
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}
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let Latency = 6 in {
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let Latency = 5 in {
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def : WriteRes<WriteFLD16, [SiFiveP600LDST]>;
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def : WriteRes<WriteFLD32, [SiFiveP600LDST]>;
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def : WriteRes<WriteFLD64, [SiFiveP600LDST]>;

‎llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s

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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p450 -iterations=1 < %s | FileCheck %s
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lw t0, 0(a0)
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ld t0, 0(a0)
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flh ft0, 0(a0)
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flw ft0, 0(a0)
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fld ft0, 0(a0)
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 5
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# CHECK-NEXT: Total Cycles: 12
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# CHECK-NEXT: Total uOps: 5
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# CHECK: Dispatch Width: 3
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# CHECK-NEXT: uOps Per Cycle: 0.42
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# CHECK-NEXT: IPC: 0.42
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# CHECK-NEXT: Block RThroughput: 5.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 4 1.00 * lw t0, 0(a0)
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# CHECK-NEXT: 1 4 1.00 * ld t0, 0(a0)
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# CHECK-NEXT: 1 5 1.00 * flh ft0, 0(a0)
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# CHECK-NEXT: 1 5 1.00 * flw ft0, 0(a0)
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# CHECK-NEXT: 1 5 1.00 * fld ft0, 0(a0)
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFiveP400Div
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# CHECK-NEXT: [1] - SiFiveP400FEXQ0
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# CHECK-NEXT: [2] - SiFiveP400FloatDiv
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# CHECK-NEXT: [3] - SiFiveP400IEXQ0
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# CHECK-NEXT: [4] - SiFiveP400IEXQ1
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# CHECK-NEXT: [5] - SiFiveP400IEXQ2
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# CHECK-NEXT: [6] - SiFiveP400Load
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# CHECK-NEXT: [7] - SiFiveP400Store
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - - - - - 5.00 -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - - - - - 1.00 - lw t0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - ld t0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - flh ft0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - flw ft0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - fld ft0, 0(a0)

‎llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,64 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
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lw t0, 0(a0)
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ld t0, 0(a0)
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flh ft0, 0(a0)
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flw ft0, 0(a0)
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fld ft0, 0(a0)
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 5
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# CHECK-NEXT: Total Cycles: 10
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# CHECK-NEXT: Total uOps: 5
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# CHECK: Dispatch Width: 4
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# CHECK-NEXT: uOps Per Cycle: 0.50
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# CHECK-NEXT: IPC: 0.50
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# CHECK-NEXT: Block RThroughput: 2.5
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 4 0.50 * lw t0, 0(a0)
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# CHECK-NEXT: 1 4 0.50 * ld t0, 0(a0)
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# CHECK-NEXT: 1 5 0.50 * flh ft0, 0(a0)
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# CHECK-NEXT: 1 5 0.50 * flw ft0, 0(a0)
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# CHECK-NEXT: 1 5 0.50 * fld ft0, 0(a0)
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFiveP600Div
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# CHECK-NEXT: [1] - SiFiveP600FEXQ0
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# CHECK-NEXT: [2] - SiFiveP600FEXQ1
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# CHECK-NEXT: [3] - SiFiveP600FloatDiv
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# CHECK-NEXT: [4] - SiFiveP600IEXQ0
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# CHECK-NEXT: [5] - SiFiveP600IEXQ1
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# CHECK-NEXT: [6] - SiFiveP600IEXQ2
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# CHECK-NEXT: [7] - SiFiveP600IEXQ3
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# CHECK-NEXT: [8.0] - SiFiveP600LDST
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# CHECK-NEXT: [8.1] - SiFiveP600LDST
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# CHECK-NEXT: [9] - SiFiveP600VDiv
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# CHECK-NEXT: [10] - SiFiveP600VEXQ0
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# CHECK-NEXT: [11] - SiFiveP600VEXQ1
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# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
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# CHECK-NEXT: [13] - SiFiveP600VLD
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# CHECK-NEXT: [14] - SiFiveP600VST
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
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# CHECK-NEXT: - - - - - - - - 2.00 3.00 - - - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
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# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - lw t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - ld t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - flh ft0, 0(a0)
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# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - flw ft0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - fld ft0, 0(a0)

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