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[MLIR][NVVM] Update dot.accumulate.4way NVVM Op (#141223)
This change refactors and updates the `dot.accumulate.4way` NVVM Op to be more descriptive and readable.
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-53
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lines changed

‎mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -3640,36 +3640,38 @@ def NVVM_Tcgen05StOp : NVVM_Op<"tcgen05.st", [NVVMRequiresSMa<[100, 101]>]> {
36403640
}
36413641

36423642
//===----------------------------------------------------------------------===//
3643-
// NVVM dot.accumulate.4way Op
3643+
// NVVM dot.accumulate Ops
36443644
//===----------------------------------------------------------------------===//
36453645

3646-
def DotAccumulate4WayS8 : I32EnumAttrCase<"S8", 1, "s8">;
3647-
def DotAccumulate4WayU8 : I32EnumAttrCase<"U8", 0, "u8">;
3646+
def DotAccumulateUnsigned : I32EnumAttrCase<"UNSIGNED", 0, "unsigned">;
3647+
def DotAccumulateSigned : I32EnumAttrCase<"SIGNED", 1, "signed">;
36483648

3649-
def DotAccumulate4WayType : I32EnumAttr<"DotAccumulate4WayType",
3650-
"NVVM DotAccumulate4WayType",
3651-
[DotAccumulate4WayS8, DotAccumulate4WayU8]> {
3649+
def DotAccumulateType : I32EnumAttr<"DotAccumulateType",
3650+
"NVVM DotAccumulateType",
3651+
[DotAccumulateSigned, DotAccumulateUnsigned]> {
36523652
let cppNamespace = "::mlir::NVVM";
36533653
let genSpecializedAttr = 0;
36543654
}
36553655

3656-
def DotAccumulate4WayTypeAttr : EnumAttr<NVVM_Dialect, DotAccumulate4WayType, "dot_accumulate_4way_type"> {
3656+
def DotAccumulateTypeAttr : EnumAttr<NVVM_Dialect, DotAccumulateType, "dot_accumulate_type"> {
36573657
let assemblyFormat = "`<` $value `>`";
36583658
}
36593659

36603660
def NVVM_DotAccumulate4WayOp : NVVM_Op<"dot.accumulate.4way"> {
3661-
let summary = "Four-way byte dot product-accumulate instruction.";
3661+
let summary = "Four-way byte dot product-accumulate instruction";
36623662
let description = [{
36633663
Performs a four-way byte dot-product which is accumulated in a 32-bit
36643664
result.
36653665
Operand `a` and `b` are vectors of 4 bytes between which the dot product is
36663666
computed.
3667+
36673668
The `a_type` and `b_type` attributes specify the type of the elements in `a`
36683669
and `b` respectively.
3669-
If `a_type` or `b_type` is `s8`, then the elements in the corresponding
3670+
If `a_type` or `b_type` is `signed`, then the elements in the corresponding
36703671
vector are sign-extended to 32-bit before the dot product is computed.
3671-
If `a_type` or `b_type` is `u8`, then the elements in the corresponding
3672-
vector are zero-extended to 32-bit instead.
3672+
If `a_type` or `b_type` is `unsigned`, then the elements in the
3673+
corresponding vector are zero-extended to 32-bit instead.
3674+
36733675
Operand `c` is a 32-bit integer to which the result is accumulated. It is
36743676
treated as holding a signed integer if any of `a_type` or `b_type` is `s8`.
36753677

@@ -3678,9 +3680,9 @@ def NVVM_DotAccumulate4WayOp : NVVM_Op<"dot.accumulate.4way"> {
36783680

36793681
let arguments = (ins
36803682
VectorOfLengthAndType<[4], [I8]>:$a,
3681-
DotAccumulate4WayTypeAttr:$a_type,
3683+
DotAccumulateTypeAttr:$a_type,
36823684
VectorOfLengthAndType<[4], [I8]>:$b,
3683-
DotAccumulate4WayTypeAttr:$b_type,
3685+
DotAccumulateTypeAttr:$b_type,
36843686
I32:$c
36853687
);
36863688

@@ -3689,17 +3691,15 @@ def NVVM_DotAccumulate4WayOp : NVVM_Op<"dot.accumulate.4way"> {
36893691
let assemblyFormat = "$a $a_type `,` $b $b_type `,` $c attr-dict `:` type($a) `,` type($b)";
36903692

36913693
let extraClassDeclaration = [{
3692-
static llvm::Intrinsic::ID
3693-
getIntrinsicID(NVVM::DotAccumulate4WayType a_type,
3694-
NVVM::DotAccumulate4WayType b_type);
3695-
llvm::Value* getPackedArg(llvm::Value* arg, llvm::IRBuilderBase& builder);
3694+
static mlir::NVVM::IDArgPair
3695+
getIntrinsicIDAndArgs(Operation &op, LLVM::ModuleTranslation &mt,
3696+
llvm::IRBuilderBase &builder);
36963697
}];
36973698

36983699
string llvmBuilder = [{
3699-
llvm::Intrinsic::ID id = NVVM::DotAccumulate4WayOp::getIntrinsicID($a_type, $b_type);
3700-
llvm::Value* argA = op.getPackedArg($a, builder);
3701-
llvm::Value* argB = op.getPackedArg($b, builder);
3702-
$res = createIntrinsicCall(builder, id, {argA, argB, $c});
3700+
auto [id, args] = NVVM::DotAccumulate4WayOp::getIntrinsicIDAndArgs(
3701+
*op, moduleTranslation, builder);
3702+
$res = createIntrinsicCall(builder, id, args);
37033703
}];
37043704
}
37053705

‎mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1205,13 +1205,6 @@ LogicalResult NVVM::VoteSyncOp::verify() {
12051205
return success();
12061206
}
12071207

1208-
llvm::Value *
1209-
NVVM::DotAccumulate4WayOp::getPackedArg(llvm::Value *arg,
1210-
llvm::IRBuilderBase &builder) {
1211-
return builder.CreateBitCast(arg,
1212-
llvm::Type::getInt32Ty(builder.getContext()));
1213-
}
1214-
12151208
/// Packs the given `field` into the `result`.
12161209
/// The `result` is 64-bits and each `field` can be 32-bits or narrower.
12171210
static llvm::Value *
@@ -1692,24 +1685,31 @@ static void nvvmInferResultRanges(Operation *op, Value result,
16921685
}
16931686
}
16941687

1695-
llvm::Intrinsic::ID
1696-
DotAccumulate4WayOp::getIntrinsicID(NVVM::DotAccumulate4WayType a_type,
1697-
NVVM::DotAccumulate4WayType b_type) {
1698-
bool is_a_siext = a_type == NVVM::DotAccumulate4WayType::S8;
1699-
bool is_b_siext = b_type == NVVM::DotAccumulate4WayType::S8;
1700-
unsigned type = (is_a_siext << 1) | is_b_siext;
1701-
switch (type) {
1702-
case 0:
1703-
return llvm::Intrinsic::nvvm_idp4a_u_u;
1704-
case 1:
1705-
return llvm::Intrinsic::nvvm_idp4a_u_s;
1706-
case 2:
1707-
return llvm::Intrinsic::nvvm_idp4a_s_u;
1708-
case 3:
1709-
return llvm::Intrinsic::nvvm_idp4a_s_s;
1710-
default:
1711-
llvm_unreachable("Invalid DP4a type");
1712-
}
1688+
static llvm::Value *getAsPackedI32(llvm::Value *arg,
1689+
llvm::IRBuilderBase &builder) {
1690+
return builder.CreateBitCast(arg,
1691+
llvm::Type::getInt32Ty(builder.getContext()));
1692+
}
1693+
1694+
NVVM::IDArgPair DotAccumulate4WayOp::getIntrinsicIDAndArgs(
1695+
Operation &op, LLVM::ModuleTranslation &mt, llvm::IRBuilderBase &builder) {
1696+
auto curOp = cast<NVVM::DotAccumulate4WayOp>(op);
1697+
1698+
llvm::SmallVector<llvm::Value *> args;
1699+
args.push_back(getAsPackedI32(mt.lookupValue(curOp.getA()), builder));
1700+
args.push_back(getAsPackedI32(mt.lookupValue(curOp.getB()), builder));
1701+
args.push_back(mt.lookupValue(curOp.getC()));
1702+
1703+
bool isASigned = curOp.getAType() == NVVM::DotAccumulateType::SIGNED;
1704+
bool isBSigned = curOp.getBType() == NVVM::DotAccumulateType::SIGNED;
1705+
unsigned type = (isASigned << 1) | isBSigned;
1706+
const llvm::Intrinsic::ID ids[] = {
1707+
llvm::Intrinsic::nvvm_idp4a_u_u,
1708+
llvm::Intrinsic::nvvm_idp4a_u_s,
1709+
llvm::Intrinsic::nvvm_idp4a_s_u,
1710+
llvm::Intrinsic::nvvm_idp4a_s_s,
1711+
};
1712+
return {ids[type], args};
17131713
}
17141714

17151715
//===----------------------------------------------------------------------===//

‎mlir/test/Dialect/LLVMIR/nvvm.mlir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -579,11 +579,11 @@ func.func @st_bulk(%addr_gen: !llvm.ptr, %addr_shared: !llvm.ptr<3>, %size: i64)
579579
}
580580

581581
// CHECK-LABEL: @dot_accumulate_4way
582-
func.func @dot_accumulate_4way(%a: i32, %a_vec: vector<4xi8>, %b: i32, %b_vec: vector<4xi8>, %c: i32) {
582+
func.func @dot_accumulate_4way(%a_vec: vector<4xi8>, %b_vec: vector<4xi8>, %c: i32) {
583583
// CHECK: nvvm.dot.accumulate.4way %{{.*}}, %{{.*}}, %{{.*}} : vector<4xi8>, vector<4xi8>
584-
%1 = nvvm.dot.accumulate.4way %a_vec <u8>, %b_vec <u8>, %c: vector<4xi8>, vector<4xi8>
584+
%1 = nvvm.dot.accumulate.4way %a_vec <unsigned>, %b_vec <unsigned>, %c: vector<4xi8>, vector<4xi8>
585585
// CHECK: nvvm.dot.accumulate.4way %{{.*}}, %{{.*}}, %{{.*}} : vector<4xi8>, vector<4xi8>
586-
%3 = nvvm.dot.accumulate.4way %a_vec <s8>, %b_vec <s8>, %c: vector<4xi8>, vector<4xi8>
586+
%3 = nvvm.dot.accumulate.4way %a_vec <signed>, %b_vec <signed>, %c: vector<4xi8>, vector<4xi8>
587587
return
588588
}
589589

‎mlir/test/Target/LLVMIR/nvvmir.mlir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -851,18 +851,18 @@ llvm.func @nvvm_dot_accumulate_4way(%a: vector<4xi8>, %b: vector<4xi8>, %c: i32)
851851
// CHECK: %[[a_cast:.*]] = bitcast <4 x i8> %{{.*}} to i32
852852
// CHECK: %[[b_cast:.*]] = bitcast <4 x i8> %{{.*}} to i32
853853
// CHECK: call i32 @llvm.nvvm.idp4a.u.u(i32 %[[a_cast]], i32 %[[b_cast]], i32 %{{.*}})
854-
%0 = nvvm.dot.accumulate.4way %a <u8>, %b <u8>, %c: vector<4xi8>, vector<4xi8>
854+
%0 = nvvm.dot.accumulate.4way %a <unsigned>, %b <unsigned>, %c: vector<4xi8>, vector<4xi8>
855855
// CHECK: %[[a_cast:.*]] = bitcast <4 x i8> %{{.*}} to i32
856856
// CHECK: %[[b_cast:.*]] = bitcast <4 x i8> %{{.*}} to i32
857857
// CHECK: call i32 @llvm.nvvm.idp4a.s.u(i32 %[[a_cast]], i32 %[[b_cast]], i32 %{{.*}})
858-
%1 = nvvm.dot.accumulate.4way %a <s8>, %b <u8>, %c: vector<4xi8>, vector<4xi8>
858+
%1 = nvvm.dot.accumulate.4way %a <signed>, %b <unsigned>, %c: vector<4xi8>, vector<4xi8>
859859
// CHECK: %[[a_cast:.*]] = bitcast <4 x i8> %{{.*}} to i32
860860
// CHECK: %[[b_cast:.*]] = bitcast <4 x i8> %{{.*}} to i32
861861
// CHECK: call i32 @llvm.nvvm.idp4a.u.s(i32 %[[a_cast]], i32 %[[b_cast]], i32 %{{.*}})
862-
%2 = nvvm.dot.accumulate.4way %a <u8>, %b <s8>, %c: vector<4xi8>, vector<4xi8>
862+
%2 = nvvm.dot.accumulate.4way %a <unsigned>, %b <signed>, %c: vector<4xi8>, vector<4xi8>
863863
// CHECK: %[[a_cast:.*]] = bitcast <4 x i8> %{{.*}} to i32
864864
// CHECK: %[[b_cast:.*]] = bitcast <4 x i8> %{{.*}} to i32
865865
// CHECK: call i32 @llvm.nvvm.idp4a.s.s(i32 %[[a_cast]], i32 %[[b_cast]], i32 %{{.*}})
866-
%3 = nvvm.dot.accumulate.4way %a <s8>, %b <s8>, %c: vector<4xi8>, vector<4xi8>
866+
%3 = nvvm.dot.accumulate.4way %a <signed>, %b <signed>, %c: vector<4xi8>, vector<4xi8>
867867
llvm.return
868868
}

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