Skip to content

Commit 61726ad

Browse files
LukacmaLukacma
authored
[AArch64] Update predicate for FEXPA (#116613)
This patch updates predicate and backend tests for FEXPA instructions to match [latest spec](https://developer.arm.com/documentation/ddi0602/2024-09/SVE-Instructions/FEXPA--Floating-point-exponential-accelerator-).
1 parent b2ec416 commit 61726ad

File tree

4 files changed

+36
-39
lines changed

4 files changed

+36
-39
lines changed

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -971,7 +971,7 @@ let Predicates = [HasSVEorSME] in {
971971
def MOVPRFX_ZZ : sve_int_bin_cons_misc_0_c<0b00000001, "movprfx", ZPRAny>;
972972
} // End HasSVEorSME
973973

974-
let Predicates = [HasSVE] in {
974+
let Predicates = [HasNonStreamingSVEorSME2p2] in {
975975
defm FEXPA_ZZ : sve_int_bin_cons_misc_0_c_fexpa<"fexpa", int_aarch64_sve_fexpa_x>;
976976
} // End HasSVE
977977

‎llvm/test/CodeGen/AArch64/sve-intrinsics-fexpa.ll

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -force-streaming -mattr=+sme2p2 < %s | FileCheck %s
4+
5+
define <vscale x 8 x half> @fexpa_h(<vscale x 8 x i16> %a) {
6+
; CHECK-LABEL: fexpa_h:
7+
; CHECK: // %bb.0:
8+
; CHECK-NEXT: fexpa z0.h, z0.h
9+
; CHECK-NEXT: ret
10+
%out = call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> %a)
11+
ret <vscale x 8 x half> %out
12+
}
13+
14+
define <vscale x 4 x float> @fexpa_s(<vscale x 4 x i32> %a) {
15+
; CHECK-LABEL: fexpa_s:
16+
; CHECK: // %bb.0:
17+
; CHECK-NEXT: fexpa z0.s, z0.s
18+
; CHECK-NEXT: ret
19+
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> %a)
20+
ret <vscale x 4 x float> %out
21+
}
22+
23+
define <vscale x 2 x double> @fexpa_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
24+
; CHECK-LABEL: fexpa_d:
25+
; CHECK: // %bb.0:
26+
; CHECK-NEXT: fexpa z0.d, z0.d
27+
; CHECK-NEXT: ret
28+
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> %a)
29+
ret <vscale x 2 x double> %out
30+
}

‎llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll

Lines changed: 0 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -299,37 +299,6 @@ define <vscale x 2 x double> @fdivr_d(<vscale x 2 x i1> %pg, <vscale x 2 x doubl
299299
ret <vscale x 2 x double> %out
300300
}
301301

302-
;
303-
; FEXPA
304-
;
305-
306-
define <vscale x 8 x half> @fexpa_h(<vscale x 8 x i16> %a) {
307-
; CHECK-LABEL: fexpa_h:
308-
; CHECK: // %bb.0:
309-
; CHECK-NEXT: fexpa z0.h, z0.h
310-
; CHECK-NEXT: ret
311-
%out = call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> %a)
312-
ret <vscale x 8 x half> %out
313-
}
314-
315-
define <vscale x 4 x float> @fexpa_s(<vscale x 4 x i32> %a) {
316-
; CHECK-LABEL: fexpa_s:
317-
; CHECK: // %bb.0:
318-
; CHECK-NEXT: fexpa z0.s, z0.s
319-
; CHECK-NEXT: ret
320-
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> %a)
321-
ret <vscale x 4 x float> %out
322-
}
323-
324-
define <vscale x 2 x double> @fexpa_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
325-
; CHECK-LABEL: fexpa_d:
326-
; CHECK: // %bb.0:
327-
; CHECK-NEXT: fexpa z0.d, z0.d
328-
; CHECK-NEXT: ret
329-
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> %a)
330-
ret <vscale x 2 x double> %out
331-
}
332-
333302
;
334303
; FMAD
335304
;
@@ -1668,10 +1637,6 @@ declare <vscale x 8 x half> @llvm.aarch64.sve.fdivr.nxv8f16(<vscale x 8 x i1>, <
16681637
declare <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
16691638
declare <vscale x 2 x double> @llvm.aarch64.sve.fdivr.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
16701639

1671-
declare <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16>)
1672-
declare <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32>)
1673-
declare <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64>)
1674-
16751640
declare <vscale x 8 x half> @llvm.aarch64.sve.fmad.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)
16761641
declare <vscale x 4 x float> @llvm.aarch64.sve.fmad.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
16771642
declare <vscale x 2 x double> @llvm.aarch64.sve.fmad.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)

‎llvm/test/MC/AArch64/SVE/fexpa.s

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
22
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
35
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
46
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
57
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
@@ -12,17 +14,17 @@
1214
fexpa z0.h, z31.h
1315
// CHECK-INST: fexpa z0.h, z31.h
1416
// CHECK-ENCODING: [0xe0,0xbb,0x60,0x04]
15-
// CHECK-ERROR: instruction requires: sve
17+
// CHECK-ERROR: instruction requires: sve or sme2p2
1618
// CHECK-UNKNOWN: 0460bbe0 <unknown>
1719

1820
fexpa z0.s, z31.s
1921
// CHECK-INST: fexpa z0.s, z31.s
2022
// CHECK-ENCODING: [0xe0,0xbb,0xa0,0x04]
21-
// CHECK-ERROR: instruction requires: sve
23+
// CHECK-ERROR: instruction requires: sve or sme2p2
2224
// CHECK-UNKNOWN: 04a0bbe0 <unknown>
2325

2426
fexpa z0.d, z31.d
2527
// CHECK-INST: fexpa z0.d, z31.d
2628
// CHECK-ENCODING: [0xe0,0xbb,0xe0,0x04]
27-
// CHECK-ERROR: instruction requires: sve
29+
// CHECK-ERROR: instruction requires: sve or sme2p2
2830
// CHECK-UNKNOWN: 04e0bbe0 <unknown>

0 commit comments

Comments
 (0)