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sdesmalen-armsdesmalen-arm
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+63
-61
lines changed

3 files changed

+63
-61
lines changed

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -424,7 +424,7 @@ AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
424424
return {};
425425
}
426426

427-
static SmallVector<MCPhysReg> ReservedHi = {
427+
static MCPhysReg ReservedHi[] = {
428428
AArch64::B0_HI, AArch64::B1_HI, AArch64::B2_HI, AArch64::B3_HI,
429429
AArch64::B4_HI, AArch64::B5_HI, AArch64::B6_HI, AArch64::B7_HI,
430430
AArch64::B8_HI, AArch64::B9_HI, AArch64::B10_HI, AArch64::B11_HI,
@@ -473,8 +473,7 @@ static SmallVector<MCPhysReg> ReservedHi = {
473473
AArch64::W20_HI, AArch64::W21_HI, AArch64::W22_HI, AArch64::W23_HI,
474474
AArch64::W24_HI, AArch64::W25_HI, AArch64::W26_HI, AArch64::W27_HI,
475475
AArch64::W28_HI, AArch64::W29_HI, AArch64::W30_HI, AArch64::WSP_HI,
476-
AArch64::WZR_HI
477-
};
476+
AArch64::WZR_HI};
478477

479478
BitVector
480479
AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {

‎llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp

Lines changed: 61 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1+
#include "AArch64RegisterInfo.h"
12
#include "AArch64InstrInfo.h"
23
#include "AArch64Subtarget.h"
34
#include "AArch64TargetMachine.h"
4-
#include "AArch64RegisterInfo.h"
55
#include "llvm/MC/MCSubtargetInfo.h"
66
#include "llvm/MC/TargetRegistry.h"
77
#include "llvm/Support/TargetSelect.h"
@@ -51,98 +51,102 @@ TEST(AArch64LaneBitmasks, SubRegs) {
5151

5252
// Test that the lane masks for the subregisters 'bsub, hsub, ssub, etc'
5353
// are composed correctly.
54-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::bsub) |
55-
TRI.getSubRegIndexLaneMask(AArch64::bsub_hi),
54+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::bsub) |
55+
TRI.getSubRegIndexLaneMask(AArch64::bsub_hi),
5656
TRI.getSubRegIndexLaneMask(AArch64::hsub));
5757

58-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::hsub) |
59-
TRI.getSubRegIndexLaneMask(AArch64::hsub_hi),
58+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::hsub) |
59+
TRI.getSubRegIndexLaneMask(AArch64::hsub_hi),
6060
TRI.getSubRegIndexLaneMask(AArch64::ssub));
6161

62-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::ssub) |
63-
TRI.getSubRegIndexLaneMask(AArch64::ssub_hi),
62+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::ssub) |
63+
TRI.getSubRegIndexLaneMask(AArch64::ssub_hi),
6464
TRI.getSubRegIndexLaneMask(AArch64::dsub));
6565

66-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub) |
67-
TRI.getSubRegIndexLaneMask(AArch64::dsub_hi),
66+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub) |
67+
TRI.getSubRegIndexLaneMask(AArch64::dsub_hi),
6868
TRI.getSubRegIndexLaneMask(AArch64::zsub));
6969

70-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub) |
71-
TRI.getSubRegIndexLaneMask(AArch64::zsub_hi),
70+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub) |
71+
TRI.getSubRegIndexLaneMask(AArch64::zsub_hi),
7272
TRI.getSubRegIndexLaneMask(AArch64::zsub0));
7373

7474
// Test that the lane masks for tuples are composed correctly.
75-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub) |
76-
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub_hi),
75+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub) |
76+
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub_hi),
7777
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub));
7878

79-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub) |
80-
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub_hi),
79+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub) |
80+
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub_hi),
8181
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub));
8282

83-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub) |
84-
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub_hi),
83+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub) |
84+
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub_hi),
8585
TRI.getSubRegIndexLaneMask(AArch64::dsub1));
8686

87-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1) |
88-
TRI.getSubRegIndexLaneMask(AArch64::qsub1_then_dsub_hi),
87+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1) |
88+
TRI.getSubRegIndexLaneMask(AArch64::qsub1_then_dsub_hi),
8989
TRI.getSubRegIndexLaneMask(AArch64::qsub1));
9090

91-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sub_32) |
92-
TRI.getSubRegIndexLaneMask(AArch64::sub_32_hi),
91+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sub_32) |
92+
TRI.getSubRegIndexLaneMask(AArch64::sub_32_hi),
9393
TRI.getSubRegIndexLaneMask(AArch64::sube64));
9494

95-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32) |
96-
TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32_hi),
95+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32) |
96+
TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32_hi),
9797
TRI.getSubRegIndexLaneMask(AArch64::subo64));
9898

9999
// Test that there is no overlap between different (sub)registers
100100
// in a tuple.
101-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub0) &
102-
TRI.getSubRegIndexLaneMask(AArch64::dsub1) &
103-
TRI.getSubRegIndexLaneMask(AArch64::dsub2) &
104-
TRI.getSubRegIndexLaneMask(AArch64::dsub3),
101+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub0) &
102+
TRI.getSubRegIndexLaneMask(AArch64::dsub1) &
103+
TRI.getSubRegIndexLaneMask(AArch64::dsub2) &
104+
TRI.getSubRegIndexLaneMask(AArch64::dsub3),
105105
LaneBitmask::getNone());
106106

107-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::qsub0) &
108-
TRI.getSubRegIndexLaneMask(AArch64::qsub1) &
109-
TRI.getSubRegIndexLaneMask(AArch64::qsub2) &
110-
TRI.getSubRegIndexLaneMask(AArch64::qsub3),
107+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::qsub0) &
108+
TRI.getSubRegIndexLaneMask(AArch64::qsub1) &
109+
TRI.getSubRegIndexLaneMask(AArch64::qsub2) &
110+
TRI.getSubRegIndexLaneMask(AArch64::qsub3),
111111
LaneBitmask::getNone());
112112

113-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub0) &
114-
TRI.getSubRegIndexLaneMask(AArch64::zsub1) &
115-
TRI.getSubRegIndexLaneMask(AArch64::zsub2) &
116-
TRI.getSubRegIndexLaneMask(AArch64::zsub3),
113+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub0) &
114+
TRI.getSubRegIndexLaneMask(AArch64::zsub1) &
115+
TRI.getSubRegIndexLaneMask(AArch64::zsub2) &
116+
TRI.getSubRegIndexLaneMask(AArch64::zsub3),
117117
LaneBitmask::getNone());
118118

119-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube32) &
120-
TRI.getSubRegIndexLaneMask(AArch64::subo32),
119+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube32) &
120+
TRI.getSubRegIndexLaneMask(AArch64::subo32),
121121
LaneBitmask::getNone());
122122

123-
ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube64) &
124-
TRI.getSubRegIndexLaneMask(AArch64::subo64),
123+
EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube64) &
124+
TRI.getSubRegIndexLaneMask(AArch64::subo64),
125125
LaneBitmask::getNone());
126126

127127
// Test that getting a subregister results in the expected subregister.
128-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::bsub), AArch64::B0);
129-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::hsub), AArch64::H0);
130-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::ssub), AArch64::S0);
131-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub), AArch64::D0);
132-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub), AArch64::Q0);
133-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub0), AArch64::Z0);
134-
135-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_bsub), AArch64::B8);
136-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_hsub), AArch64::H8);
137-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_ssub), AArch64::S8);
138-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1), AArch64::D8);
139-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::qsub1), AArch64::Q8);
140-
ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub1), AArch64::Z8);
141-
142-
ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sube64), AArch64::X0);
143-
ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64), AArch64::X1);
144-
ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sub_32), AArch64::W0);
145-
ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64_then_sub_32), AArch64::W1);
128+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::bsub), AArch64::B0);
129+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::hsub), AArch64::H0);
130+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::ssub), AArch64::S0);
131+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub), AArch64::D0);
132+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub), AArch64::Q0);
133+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub0), AArch64::Z0);
134+
135+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_bsub),
136+
AArch64::B8);
137+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_hsub),
138+
AArch64::H8);
139+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_ssub),
140+
AArch64::S8);
141+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1), AArch64::D8);
142+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::qsub1), AArch64::Q8);
143+
EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub1), AArch64::Z8);
144+
145+
EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sube64), AArch64::X0);
146+
EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64), AArch64::X1);
147+
EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sub_32), AArch64::W0);
148+
EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64_then_sub_32),
149+
AArch64::W1);
146150
}
147151

148152
} // namespace

‎llvm/utils/TableGen/RegisterInfoEmitter.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1841,7 +1841,6 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
18411841
OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';
18421842
OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n';
18431843
OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n';
1844-
OS << "\tArtificial: " << RC.Artificial << '\n';
18451844
OS << "\tAllocatable: " << RC.Allocatable << '\n';
18461845
OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n';
18471846
OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n';

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