Skip to content

Commit 6206d7d

Browse files
authored
[X86] combineConstantPoolLoads - correctly merge constant pool loads by pointer and chain (#139575)
We were merging with a larger constant pool load if it didn't have any chain dependencies (and implicitly assuming all uses were on the vector value), instead we should flip this, explicitly check for uses of the vector value and merge the memory chain dependencies with makeEquivalentMemoryOrdering. As these are constant pool loads we shouldn't expect any changes here, but we should be consistent with how we merge/reuse loads - an upcoming patch for other loads will do the same as we will see changes there.
1 parent 06f779b commit 6206d7d

File tree

1 file changed

+2
-1
lines changed

1 file changed

+2
-1
lines changed

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53035,7 +53035,7 @@ static SDValue combineConstantPoolLoads(SDNode *N, const SDLoc &dl,
5303553035
(User->getOpcode() == X86ISD::SUBV_BROADCAST_LOAD ||
5303653036
User->getOpcode() == X86ISD::VBROADCAST_LOAD ||
5303753037
ISD::isNormalLoad(User)) &&
53038-
UserLd->getChain() == Chain && !User->hasAnyUseOfValue(1) &&
53038+
UserLd->getChain() == Chain && User->hasAnyUseOfValue(0) &&
5303953039
User->getValueSizeInBits(0).getFixedValue() >
5304053040
RegVT.getFixedSizeInBits()) {
5304153041
EVT UserVT = User->getValueType(0);
@@ -53057,6 +53057,7 @@ static SDValue combineConstantPoolLoads(SDNode *N, const SDLoc &dl,
5305753057
getTargetConstantBitsFromNode(SDValue(User, 0), NumBits,
5305853058
UserUndefs, UserBits)) {
5305953059
if (MatchingBits(Undefs, UserUndefs, Bits, UserBits)) {
53060+
DAG.makeEquivalentMemoryOrdering(SDValue(N, 1), SDValue(User, 1));
5306053061
SDValue Extract = extractSubVector(SDValue(User, 0), 0, DAG, dl,
5306153062
RegVT.getSizeInBits());
5306253063
Extract = DAG.getBitcast(RegVT, Extract);

0 commit comments

Comments
 (0)