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[DAG] Use SDValue for PatFrag checks
If the SDNode is used it can pick up the wrong results number, for example looking at the known bits of the first result where it should be looking at the second. The SDValue is already present as the SelectCodeCommon checks move from parent to child, pass the SDValue through to CheckNodePredicate as Op so that it can use it if necessary. SDNode *N is still generated, keeping most PatFrags the same. Fixes #137274
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16 files changed

+61
-46
lines changed

16 files changed

+61
-46
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAGISel.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -426,7 +426,7 @@ class SelectionDAGISel {
426426
/// It runs node predicate number PredNo and returns true if it succeeds or
427427
/// false if it fails. The number is a private implementation
428428
/// detail to the code tblgen produces.
429-
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
429+
virtual bool CheckNodePredicate(SDValue Op, unsigned PredNo) const {
430430
llvm_unreachable("Tblgen should generate the implementation of this!");
431431
}
432432

@@ -436,7 +436,7 @@ class SelectionDAGISel {
436436
/// false if it fails. The number is a private implementation detail to the
437437
/// code tblgen produces.
438438
virtual bool CheckNodePredicateWithOperands(
439-
SDNode *N, unsigned PredNo,
439+
SDValue Op, unsigned PredNo,
440440
const SmallVectorImpl<SDValue> &Operands) const {
441441
llvm_unreachable("Tblgen should generate the implementation of this!");
442442
}

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2897,11 +2897,11 @@ CheckPatternPredicate(unsigned Opcode, const unsigned char *MatcherTable,
28972897
LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
28982898
CheckNodePredicate(unsigned Opcode, const unsigned char *MatcherTable,
28992899
unsigned &MatcherIndex, const SelectionDAGISel &SDISel,
2900-
SDNode *N) {
2900+
SDValue Op) {
29012901
unsigned PredNo = Opcode == SelectionDAGISel::OPC_CheckPredicate
29022902
? MatcherTable[MatcherIndex++]
29032903
: Opcode - SelectionDAGISel::OPC_CheckPredicate0;
2904-
return SDISel.CheckNodePredicate(N, PredNo);
2904+
return SDISel.CheckNodePredicate(Op, PredNo);
29052905
}
29062906

29072907
LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
@@ -3062,7 +3062,7 @@ static unsigned IsPredicateKnownToFail(const unsigned char *Table,
30623062
case SelectionDAGISel::OPC_CheckPredicate5:
30633063
case SelectionDAGISel::OPC_CheckPredicate6:
30643064
case SelectionDAGISel::OPC_CheckPredicate7:
3065-
Result = !::CheckNodePredicate(Opcode, Table, Index, SDISel, N.getNode());
3065+
Result = !::CheckNodePredicate(Opcode, Table, Index, SDISel, N);
30663066
return Index;
30673067
case SelectionDAGISel::OPC_CheckOpcode:
30683068
Result = !::CheckOpcode(Table, Index, N.getNode());
@@ -3575,8 +3575,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
35753575
case SelectionDAGISel::OPC_CheckPredicate6:
35763576
case SelectionDAGISel::OPC_CheckPredicate7:
35773577
case OPC_CheckPredicate:
3578-
if (!::CheckNodePredicate(Opcode, MatcherTable, MatcherIndex, *this,
3579-
N.getNode()))
3578+
if (!::CheckNodePredicate(Opcode, MatcherTable, MatcherIndex, *this, N))
35803579
break;
35813580
continue;
35823581
case OPC_CheckPredicateWithOperands: {
@@ -3587,7 +3586,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
35873586
Operands.push_back(RecordedNodes[MatcherTable[MatcherIndex++]].first);
35883587

35893588
unsigned PredNo = MatcherTable[MatcherIndex++];
3590-
if (!CheckNodePredicateWithOperands(N.getNode(), PredNo, Operands))
3589+
if (!CheckNodePredicateWithOperands(N, PredNo, Operands))
35913590
break;
35923591
continue;
35933592
}

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -683,24 +683,24 @@ defm trunc_masked_scatter_i32 : masked_gather_scatter<trunc_masked_scatter_i32>;
683683

684684
// top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
685685
def top16Zero: PatLeaf<(i32 GPR32:$src), [{
686-
return SDValue(N,0)->getValueType(0) == MVT::i32 &&
687-
CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
686+
return Op.getValueType() == MVT::i32 &&
687+
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 16));
688688
}]>;
689689

690690
// top32Zero - answer true if the upper 32 bits of $src are 0, false otherwise
691691
def top32Zero: PatLeaf<(i64 GPR64:$src), [{
692-
return SDValue(N,0)->getValueType(0) == MVT::i64 &&
693-
CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(64, 32));
692+
return Op.getValueType() == MVT::i64 &&
693+
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(64, 32));
694694
}]>;
695695

696696
// topbitsallzero - Return true if all bits except the lowest bit are known zero
697697
def topbitsallzero32: PatLeaf<(i32 GPR32:$src), [{
698-
return SDValue(N,0)->getValueType(0) == MVT::i32 &&
699-
CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 31));
698+
return Op.getValueType() == MVT::i32 &&
699+
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 31));
700700
}]>;
701701
def topbitsallzero64: PatLeaf<(i64 GPR64:$src), [{
702-
return SDValue(N,0)->getValueType(0) == MVT::i64 &&
703-
CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(64, 63));
702+
return Op.getValueType() == MVT::i64 &&
703+
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(64, 63));
704704
}]>;
705705

706706
// Node definitions.
@@ -1052,9 +1052,9 @@ def AArch64CttzElts : SDNode<"AArch64ISD::CTTZ_ELTS", SDTypeProfile<1, 1,
10521052
// have no common bits.
10531053
def add_and_or_is_add : PatFrags<(ops node:$lhs, node:$rhs),
10541054
[(add node:$lhs, node:$rhs), (or node:$lhs, node:$rhs)],[{
1055-
if (N->getOpcode() == ISD::ADD)
1055+
if (Op.getOpcode() == ISD::ADD)
10561056
return true;
1057-
return CurDAG->isADDLike(SDValue(N,0));
1057+
return CurDAG->isADDLike(Op);
10581058
}]> {
10591059
let GISelPredicateCode = [{
10601060
return mi_match(MI, MRI, m_GAddLike(m_Reg(), m_Reg()));

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -858,7 +858,7 @@ def fmaxnum_like : PatFrags<(ops node:$src0, node:$src1),
858858

859859
class NeverNaNPats<dag ops, list<dag> frags> : PatFrags<ops, frags> {
860860
let PredicateCode = [{
861-
return CurDAG->isKnownNeverNaN(SDValue(N,0));
861+
return CurDAG->isKnownNeverNaN(Op);
862862
}];
863863
let GISelPredicateCode = [{
864864
return isKnownNeverNaN(MI.getOperand(0).getReg(), MRI);

‎llvm/lib/Target/AMDGPU/R600Instructions.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -287,12 +287,12 @@ class VTX_READ <string name, dag outs, list<dag> pattern>
287287
def atomic_cmp_swap_global_noret : PatFrag<
288288
(ops node:$ptr, node:$cmp, node:$value),
289289
(atomic_cmp_swap node:$ptr, node:$cmp, node:$value),
290-
[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (SDValue(N, 0).use_empty());}]>;
290+
[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (Op.use_empty());}]>;
291291

292292
def atomic_cmp_swap_global_ret : PatFrag<
293293
(ops node:$ptr, node:$cmp, node:$value),
294294
(atomic_cmp_swap node:$ptr, node:$cmp, node:$value),
295-
[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (!SDValue(N, 0).use_empty());}]>;
295+
[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (!Op.use_empty());}]>;
296296

297297
def mskor_global : PatFrag<(ops node:$val, node:$ptr),
298298
(AMDGPUstore_mskor node:$val, node:$ptr), [{

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3861,7 +3861,7 @@ def : AMDGPUPat <
38613861
>;
38623862

38633863
def uint5Bits : PatLeaf<(i32 VGPR_32:$width), [{
3864-
return CurDAG->computeKnownBits(SDValue(N, 0)).countMaxActiveBits() <= 5;
3864+
return CurDAG->computeKnownBits(Op).countMaxActiveBits() <= 5;
38653865
}]>;
38663866

38673867
// x & (-1 >> (bitwidth - y))

‎llvm/lib/Target/ARM/ARMInstrInfo.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -421,7 +421,7 @@ def imm16_31 : ImmLeaf<i32, [{
421421

422422
// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
423423
def sext_16_node : PatLeaf<(i32 GPR:$a), [{
424-
return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
424+
return CurDAG->ComputeNumSignBits(Op) >= 17;
425425
}]>;
426426

427427
def sext_bottom_16 : PatFrag<(ops node:$a),
@@ -451,14 +451,14 @@ def lo16AllZero : PatLeaf<(i32 imm), [{
451451

452452
// top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
453453
def top16Zero: PatLeaf<(i32 GPR:$src), [{
454-
return !SDValue(N,0)->getValueType(0).isVector() &&
455-
CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
454+
return !Op.getValueType().isVector() &&
455+
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 16));
456456
}]>;
457457

458458
// topbitsallzero - Return true if all bits except the lowest bit are known zero
459459
def topbitsallzero32 : PatLeaf<(i32 GPRwithZR:$src), [{
460-
return SDValue(N,0)->getValueType(0) == MVT::i32 &&
461-
CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 31));
460+
return Op.getValueType() == MVT::i32 &&
461+
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 31));
462462
}]>;
463463

464464
class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;

‎llvm/lib/Target/BPF/BPFInstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1023,12 +1023,12 @@ foreach P = [[atomic_load_sub_i64_monotonic, XADDD],
10231023
class binop_no_use<SDPatternOperator operator>
10241024
: PatFrag<(ops node:$A, node:$B),
10251025
(operator node:$A, node:$B),
1026-
[{ return SDValue(N, 0).use_empty(); }]>;
1026+
[{ return Op.use_empty(); }]>;
10271027

10281028
class binop_has_use<SDPatternOperator operator>
10291029
: PatFrag<(ops node:$A, node:$B),
10301030
(operator node:$A, node:$B),
1031-
[{ return !SDValue(N, 0).use_empty(); }]>;
1031+
[{ return !Op.use_empty(); }]>;
10321032

10331033
foreach op = [add, and, or, xor] in {
10341034
def atomic_load_ # op # _i64_monotonic_nu:

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1337,7 +1337,7 @@ def ext_oneuse : unop_oneuse<ext>;
13371337
def fpext_oneuse : unop_oneuse<any_fpextend>;
13381338

13391339
def 33signbits_node : PatLeaf<(i64 GPR:$src), [{
1340-
return CurDAG->ComputeNumSignBits(SDValue(N, 0)) > 32;
1340+
return CurDAG->ComputeNumSignBits(Op) > 32;
13411341
}]>;
13421342

13431343
class immop_oneuse<ImmLeaf leaf> : PatLeaf<(leaf), [{
@@ -1977,7 +1977,7 @@ def : Pat<(i64 (shl (and GPR:$rs1, 0xffffffff), uimm5:$shamt)),
19771977
class binop_allhusers<SDPatternOperator operator>
19781978
: PatFrag<(ops node:$lhs, node:$rhs),
19791979
(XLenVT (operator node:$lhs, node:$rhs)), [{
1980-
return hasAllHUsers(Node);
1980+
return hasAllHUsers(N);
19811981
}]> {
19821982
let GISelPredicateCode = [{ return hasAllHUsers(MI); }];
19831983
}
@@ -1987,14 +1987,14 @@ class binop_allhusers<SDPatternOperator operator>
19871987
class binop_allwusers<SDPatternOperator operator>
19881988
: PatFrag<(ops node:$lhs, node:$rhs), (i64 (operator node:$lhs, node:$rhs)),
19891989
[{
1990-
return hasAllWUsers(Node);
1990+
return hasAllWUsers(N);
19911991
}]> {
19921992
let GISelPredicateCode = [{ return hasAllWUsers(MI); }];
19931993
}
19941994

19951995
def sexti32_allwusers : PatFrag<(ops node:$src),
19961996
(sext_inreg node:$src, i32), [{
1997-
return hasAllWUsers(Node);
1997+
return hasAllWUsers(N);
19981998
}]>;
19991999

20002000
def ImmSExt32 : SDNodeXForm<imm, [{

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,7 @@ def TypeIndex : Operand<i32>;
239239

240240
// TODO: Find more places to use this.
241241
def bool_node : PatLeaf<(i32 I32:$cond), [{
242-
return CurDAG->computeKnownBits(SDValue(N, 0)).countMinLeadingZeros() == 31;
242+
return CurDAG->computeKnownBits(Op).countMinLeadingZeros() == 31;
243243
}]>;
244244

245245
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5705,7 +5705,7 @@ let Predicates = [UseSSE41, OptForSize] in {
57055705
// commuting would change which operand is inverted.
57065706
def X86ptest_commutable : PatFrag<(ops node:$src1, node:$src2),
57075707
(X86ptest node:$src1, node:$src2), [{
5708-
return onlyUsesZeroFlag(SDValue(Node, 0));
5708+
return onlyUsesZeroFlag(Op);
57095709
}]>;
57105710

57115711
// ptest instruction we'll lower to this in X86ISelLowering primarily from
@@ -5772,7 +5772,7 @@ multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
57725772
// used, commuting would change which operand is inverted.
57735773
def X86testp_commutable : PatFrag<(ops node:$src1, node:$src2),
57745774
(X86testp node:$src1, node:$src2), [{
5775-
return onlyUsesZeroFlag(SDValue(Node, 0));
5775+
return onlyUsesZeroFlag(Op);
57765776
}]>;
57775777

57785778
let Defs = [EFLAGS], Predicates = [HasAVX] in {

‎llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2098,3 +2098,19 @@ B:
20982098
%t = icmp eq i64 0, %3
20992099
br i1 %t, label %A, label %B
21002100
}
2101+
2102+
define i64 @pr137274(ptr %ptr) {
2103+
; CHECK-LABEL: pr137274:
2104+
; CHECK: // %bb.0:
2105+
; CHECK-NEXT: ldr x8, [x0]
2106+
; CHECK-NEXT: ldr w9, [x8, #8]!
2107+
; CHECK-NEXT: mul x0, x8, x9
2108+
; CHECK-NEXT: ret
2109+
%l0 = load i64, ptr %ptr, align 8
2110+
%add = add i64 %l0, 8
2111+
%i1 = inttoptr i64 %add to ptr
2112+
%l2 = load i32, ptr %i1, align 4
2113+
%conv = zext i32 %l2 to i64
2114+
%mul = mul i64 %add, %conv
2115+
ret i64 %mul
2116+
}

‎llvm/test/TableGen/HasNoUse.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ def NO_RET_ATOMIC_ADD : I<(outs), (ins GPR32Op:$src0, GPR32Op:$src1), []>;
1010

1111
// SDAG: case 0: {
1212
// SDAG-NEXT: // Predicate_atomic_load_add_no_ret_i32
13-
// SDAG-NEXT: SDNode *N = Node;
13+
// SDAG-NEXT: SDNode *N = Op.getNode();
1414
// SDAG-NEXT: (void)N;
1515
// SDAG-NEXT: if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i32) return false;
1616
// SDAG-NEXT: if (N->hasAnyUseOfValue(0)) return false;

‎llvm/test/TableGen/address-space-patfrags.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ def inst_d : Instruction {
4949
// SDAG: case 0: {
5050
// SDAG-NEXT: // Predicate_pat_frag_b
5151
// SDAG-NEXT: // Predicate_truncstorei16_addrspace
52-
// SDAG-NEXT: SDNode *N = Node;
52+
// SDAG-NEXT: SDNode *N = Op.getNode();
5353
// SDAG-NEXT: (void)N;
5454
// SDAG-NEXT: unsigned AddrSpace = cast<MemSDNode>(N)->getAddressSpace();
5555
// SDAG-NEXT: if (AddrSpace != 123 && AddrSpace != 455)
@@ -71,7 +71,7 @@ def : Pat <
7171

7272
// SDAG: case 4: {
7373
// SDAG: // Predicate_pat_frag_a
74-
// SDAG-NEXT: SDNode *N = Node;
74+
// SDAG-NEXT: SDNode *N = Op.getNode();
7575
// SDAG-NEXT: (void)N;
7676
// SDAG-NEXT: if (cast<MemSDNode>(N)->getAlign() < Align(2))
7777
// SDAG-NEXT: return false;

‎llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1375,11 +1375,11 @@ std::string TreePredicateFn::getCodeToRunOnSDNode() const {
13751375

13761376
std::string Result = (" " + getImmType() + " Imm = ").str();
13771377
if (immCodeUsesAPFloat())
1378-
Result += "cast<ConstantFPSDNode>(Node)->getValueAPF();\n";
1378+
Result += "cast<ConstantFPSDNode>(Op.getNode())->getValueAPF();\n";
13791379
else if (immCodeUsesAPInt())
1380-
Result += "Node->getAsAPIntVal();\n";
1380+
Result += "Op->getAsAPIntVal();\n";
13811381
else
1382-
Result += "cast<ConstantSDNode>(Node)->getSExtValue();\n";
1382+
Result += "cast<ConstantSDNode>(Op.getNode())->getSExtValue();\n";
13831383
return Result + ImmCode;
13841384
}
13851385

@@ -1410,9 +1410,9 @@ std::string TreePredicateFn::getCodeToRunOnSDNode() const {
14101410

14111411
std::string Result;
14121412
if (ClassName == "SDNode")
1413-
Result = " SDNode *N = Node;\n";
1413+
Result = " SDNode *N = Op.getNode();\n";
14141414
else
1415-
Result = " auto *N = cast<" + ClassName.str() + ">(Node);\n";
1415+
Result = " auto *N = cast<" + ClassName.str() + ">(Op.getNode());\n";
14161416

14171417
return (Twine(Result) + " (void)N;\n" + getPredCode()).str();
14181418
}

‎llvm/utils/TableGen/DAGISelMatcherEmitter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1149,11 +1149,11 @@ void MatcherTableEmitter::EmitPredicateFunctions(raw_ostream &OS) {
11491149

11501150
// Emit Node predicates.
11511151
EmitNodePredicatesFunction(
1152-
NodePredicates, "CheckNodePredicate(SDNode *Node, unsigned PredNo) const",
1152+
NodePredicates, "CheckNodePredicate(SDValue Op, unsigned PredNo) const",
11531153
OS);
11541154
EmitNodePredicatesFunction(
11551155
NodePredicatesWithOperands,
1156-
"CheckNodePredicateWithOperands(SDNode *Node, unsigned PredNo, "
1156+
"CheckNodePredicateWithOperands(SDValue Op, unsigned PredNo, "
11571157
"const SmallVectorImpl<SDValue> &Operands) const",
11581158
OS);
11591159

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