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[LoongArch] Enable FeatureExtLSX for generic-la64 processor
This commit makes the `generic` target to support FP and LSX, as discussed in #110211. Thereby, it allows 128-bit vector to be enabled by default in the loongarch64 backend.
1 parent b799cc3 commit 622aff0

23 files changed

+548
-917
lines changed

‎llvm/lib/Target/LoongArch/LoongArch.td

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -129,7 +129,9 @@ include "LoongArchInstrInfo.td"
129129
//===----------------------------------------------------------------------===//
130130

131131
def : ProcessorModel<"generic-la32", NoSchedModel, [Feature32Bit]>;
132-
def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit, FeatureUAL]>;
132+
def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit,
133+
FeatureUAL,
134+
FeatureExtLSX]>;
133135

134136
// Generic 64-bit processor with double-precision floating-point support.
135137
def : ProcessorModel<"loongarch64", NoSchedModel, [Feature64Bit,

‎llvm/test/CodeGen/LoongArch/calling-conv-common.ll

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -123,13 +123,12 @@ define i64 @caller_large_scalars() nounwind {
123123
; CHECK-NEXT: addi.d $sp, $sp, -80
124124
; CHECK-NEXT: st.d $ra, $sp, 72 # 8-byte Folded Spill
125125
; CHECK-NEXT: st.d $zero, $sp, 24
126-
; CHECK-NEXT: st.d $zero, $sp, 16
127-
; CHECK-NEXT: st.d $zero, $sp, 8
126+
; CHECK-NEXT: vrepli.b $vr0, 0
127+
; CHECK-NEXT: vst $vr0, $sp, 8
128128
; CHECK-NEXT: ori $a0, $zero, 2
129129
; CHECK-NEXT: st.d $a0, $sp, 0
130130
; CHECK-NEXT: st.d $zero, $sp, 56
131-
; CHECK-NEXT: st.d $zero, $sp, 48
132-
; CHECK-NEXT: st.d $zero, $sp, 40
131+
; CHECK-NEXT: vst $vr0, $sp, 40
133132
; CHECK-NEXT: ori $a2, $zero, 1
134133
; CHECK-NEXT: addi.d $a0, $sp, 32
135134
; CHECK-NEXT: addi.d $a1, $sp, 0
@@ -182,14 +181,13 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
182181
; CHECK-NEXT: ori $a0, $zero, 9
183182
; CHECK-NEXT: st.d $a0, $sp, 0
184183
; CHECK-NEXT: st.d $zero, $sp, 40
185-
; CHECK-NEXT: st.d $zero, $sp, 32
186-
; CHECK-NEXT: st.d $zero, $sp, 24
184+
; CHECK-NEXT: vrepli.b $vr0, 0
185+
; CHECK-NEXT: vst $vr0, $sp, 24
187186
; CHECK-NEXT: ori $a0, $zero, 10
188187
; CHECK-NEXT: st.d $a0, $sp, 16
189188
; CHECK-NEXT: st.d $zero, $sp, 72
190-
; CHECK-NEXT: st.d $zero, $sp, 64
191-
; CHECK-NEXT: st.d $zero, $sp, 56
192-
; CHECK-NEXT: ori $t0, $zero, 8
189+
; CHECK-NEXT: ori $a0, $zero, 8
190+
; CHECK-NEXT: st.d $a0, $sp, 48
193191
; CHECK-NEXT: ori $a0, $zero, 1
194192
; CHECK-NEXT: ori $a1, $zero, 2
195193
; CHECK-NEXT: ori $a2, $zero, 3
@@ -198,7 +196,7 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
198196
; CHECK-NEXT: ori $a5, $zero, 6
199197
; CHECK-NEXT: ori $a6, $zero, 7
200198
; CHECK-NEXT: addi.d $a7, $sp, 48
201-
; CHECK-NEXT: st.d $t0, $sp, 48
199+
; CHECK-NEXT: vst $vr0, $sp, 56
202200
; CHECK-NEXT: bl %plt(callee_large_scalars_exhausted_regs)
203201
; CHECK-NEXT: ld.d $ra, $sp, 88 # 8-byte Folded Reload
204202
; CHECK-NEXT: addi.d $sp, $sp, 96

‎llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll

Lines changed: 9 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -63,26 +63,17 @@ define i64 @caller_double_in_gpr_exhausted_fprs() nounwind {
6363
; CHECK: # %bb.0:
6464
; CHECK-NEXT: addi.d $sp, $sp, -16
6565
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
66-
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
67-
; CHECK-NEXT: fld.d $fa1, $a0, %pc_lo12(.LCPI3_0)
68-
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_1)
69-
; CHECK-NEXT: fld.d $fa2, $a0, %pc_lo12(.LCPI3_1)
70-
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_2)
71-
; CHECK-NEXT: fld.d $fa3, $a0, %pc_lo12(.LCPI3_2)
72-
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_3)
73-
; CHECK-NEXT: fld.d $fa4, $a0, %pc_lo12(.LCPI3_3)
74-
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_4)
75-
; CHECK-NEXT: fld.d $fa5, $a0, %pc_lo12(.LCPI3_4)
76-
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_5)
77-
; CHECK-NEXT: fld.d $fa6, $a0, %pc_lo12(.LCPI3_5)
78-
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_6)
79-
; CHECK-NEXT: fld.d $fa7, $a0, %pc_lo12(.LCPI3_6)
80-
; CHECK-NEXT: addi.d $a0, $zero, 1
81-
; CHECK-NEXT: movgr2fr.d $fa0, $a0
82-
; CHECK-NEXT: ffint.d.l $fa0, $fa0
8366
; CHECK-NEXT: ori $a0, $zero, 0
8467
; CHECK-NEXT: lu32i.d $a0, 131072
8568
; CHECK-NEXT: lu52i.d $a0, $a0, 1026
69+
; CHECK-NEXT: vldi $vr0, -912
70+
; CHECK-NEXT: vldi $vr1, -1024
71+
; CHECK-NEXT: vldi $vr2, -1016
72+
; CHECK-NEXT: vldi $vr3, -1008
73+
; CHECK-NEXT: vldi $vr4, -1004
74+
; CHECK-NEXT: vldi $vr5, -1000
75+
; CHECK-NEXT: vldi $vr6, -996
76+
; CHECK-NEXT: vldi $vr7, -992
8677
; CHECK-NEXT: bl %plt(callee_double_in_gpr_exhausted_fprs)
8778
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
8879
; CHECK-NEXT: addi.d $sp, $sp, 16
@@ -98,9 +89,7 @@ define i64 @caller_double_in_gpr_exhausted_fprs() nounwind {
9889
define double @callee_double_ret() nounwind {
9990
; CHECK-LABEL: callee_double_ret:
10091
; CHECK: # %bb.0:
101-
; CHECK-NEXT: addi.d $a0, $zero, 1
102-
; CHECK-NEXT: movgr2fr.d $fa0, $a0
103-
; CHECK-NEXT: ffint.d.l $fa0, $fa0
92+
; CHECK-NEXT: vldi $vr0, -912
10493
; CHECK-NEXT: ret
10594
ret double 1.0
10695
}

‎llvm/test/CodeGen/LoongArch/calling-conv-lp64s.ll

Lines changed: 11 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -6,16 +6,10 @@
66
define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
77
; CHECK-LABEL: callee_float_in_regs:
88
; CHECK: # %bb.0:
9-
; CHECK-NEXT: addi.d $sp, $sp, -16
10-
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
11-
; CHECK-NEXT: st.d $fp, $sp, 0 # 8-byte Folded Spill
12-
; CHECK-NEXT: move $fp, $a0
13-
; CHECK-NEXT: move $a0, $a1
14-
; CHECK-NEXT: bl %plt(__fixsfdi)
15-
; CHECK-NEXT: add.d $a0, $fp, $a0
16-
; CHECK-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
17-
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
18-
; CHECK-NEXT: addi.d $sp, $sp, 16
9+
; CHECK-NEXT: movgr2fr.w $fa0, $a1
10+
; CHECK-NEXT: ftintrz.l.s $fa0, $fa0
11+
; CHECK-NEXT: movfr2gr.d $a1, $fa0
12+
; CHECK-NEXT: add.d $a0, $a0, $a1
1913
; CHECK-NEXT: ret
2014
%b_fptosi = fptosi float %b to i64
2115
%1 = add i64 %a, %b_fptosi
@@ -27,7 +21,8 @@ define i64 @caller_float_in_regs() nounwind {
2721
; CHECK: # %bb.0:
2822
; CHECK-NEXT: addi.d $sp, $sp, -16
2923
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
30-
; CHECK-NEXT: lu12i.w $a1, 262144
24+
; CHECK-NEXT: vldi $vr0, -1280
25+
; CHECK-NEXT: movfr2gr.s $a1, $fa0
3126
; CHECK-NEXT: ori $a0, $zero, 1
3227
; CHECK-NEXT: bl %plt(callee_float_in_regs)
3328
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
@@ -59,7 +54,7 @@ define i64 @caller_float_on_stack() nounwind {
5954
; CHECK-NEXT: ori $a2, $zero, 2
6055
; CHECK-NEXT: ori $a4, $zero, 3
6156
; CHECK-NEXT: ori $a6, $zero, 4
62-
; CHECK-NEXT: st.d $a1, $sp, 0
57+
; CHECK-NEXT: st.w $a1, $sp, 0
6358
; CHECK-NEXT: move $a1, $zero
6459
; CHECK-NEXT: move $a3, $zero
6560
; CHECK-NEXT: move $a5, $zero
@@ -75,7 +70,8 @@ define i64 @caller_float_on_stack() nounwind {
7570
define float @callee_tiny_scalar_ret() nounwind {
7671
; CHECK-LABEL: callee_tiny_scalar_ret:
7772
; CHECK: # %bb.0:
78-
; CHECK-NEXT: lu12i.w $a0, 260096
73+
; CHECK-NEXT: vldi $vr0, -1168
74+
; CHECK-NEXT: movfr2gr.s $a0, $fa0
7975
; CHECK-NEXT: ret
8076
ret float 1.0
8177
}
@@ -86,7 +82,8 @@ define i64 @caller_tiny_scalar_ret() nounwind {
8682
; CHECK-NEXT: addi.d $sp, $sp, -16
8783
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
8884
; CHECK-NEXT: bl %plt(callee_tiny_scalar_ret)
89-
; CHECK-NEXT: addi.w $a0, $a0, 0
85+
; CHECK-NEXT: movgr2fr.w $fa0, $a0
86+
; CHECK-NEXT: movfr2gr.s $a0, $fa0
9087
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
9188
; CHECK-NEXT: addi.d $sp, $sp, 16
9289
; CHECK-NEXT: ret

‎llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll

Lines changed: 19 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -175,16 +175,11 @@ define i8 @test_ctpop_i8(i8 %a) nounwind {
175175
;
176176
; LA64-LABEL: test_ctpop_i8:
177177
; LA64: # %bb.0:
178-
; LA64-NEXT: srli.d $a1, $a0, 1
179-
; LA64-NEXT: andi $a1, $a1, 85
180-
; LA64-NEXT: sub.d $a0, $a0, $a1
181-
; LA64-NEXT: andi $a1, $a0, 51
182-
; LA64-NEXT: srli.d $a0, $a0, 2
183-
; LA64-NEXT: andi $a0, $a0, 51
184-
; LA64-NEXT: add.d $a0, $a1, $a0
185-
; LA64-NEXT: srli.d $a1, $a0, 4
186-
; LA64-NEXT: add.d $a0, $a0, $a1
187-
; LA64-NEXT: andi $a0, $a0, 15
178+
; LA64-NEXT: andi $a0, $a0, 255
179+
; LA64-NEXT: vldi $vr0, 0
180+
; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
181+
; LA64-NEXT: vpcnt.d $vr0, $vr0
182+
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
188183
; LA64-NEXT: ret
189184
%1 = call i8 @llvm.ctpop.i8(i8 %a)
190185
ret i8 %1
@@ -213,22 +208,11 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
213208
;
214209
; LA64-LABEL: test_ctpop_i16:
215210
; LA64: # %bb.0:
216-
; LA64-NEXT: srli.d $a1, $a0, 1
217-
; LA64-NEXT: lu12i.w $a2, 5
218-
; LA64-NEXT: ori $a2, $a2, 1365
219-
; LA64-NEXT: and $a1, $a1, $a2
220-
; LA64-NEXT: sub.d $a0, $a0, $a1
221-
; LA64-NEXT: lu12i.w $a1, 3
222-
; LA64-NEXT: ori $a1, $a1, 819
223-
; LA64-NEXT: and $a2, $a0, $a1
224-
; LA64-NEXT: srli.d $a0, $a0, 2
225-
; LA64-NEXT: and $a0, $a0, $a1
226-
; LA64-NEXT: add.d $a0, $a2, $a0
227-
; LA64-NEXT: srli.d $a1, $a0, 4
228-
; LA64-NEXT: add.d $a0, $a0, $a1
229-
; LA64-NEXT: bstrpick.d $a1, $a0, 11, 8
230-
; LA64-NEXT: andi $a0, $a0, 15
231-
; LA64-NEXT: add.d $a0, $a0, $a1
211+
; LA64-NEXT: bstrpick.d $a0, $a0, 15, 0
212+
; LA64-NEXT: vldi $vr0, 0
213+
; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
214+
; LA64-NEXT: vpcnt.d $vr0, $vr0
215+
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
232216
; LA64-NEXT: ret
233217
%1 = call i16 @llvm.ctpop.i16(i16 %a)
234218
ret i16 %1
@@ -261,26 +245,11 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
261245
;
262246
; LA64-LABEL: test_ctpop_i32:
263247
; LA64: # %bb.0:
264-
; LA64-NEXT: srli.d $a1, $a0, 1
265-
; LA64-NEXT: lu12i.w $a2, 349525
266-
; LA64-NEXT: ori $a2, $a2, 1365
267-
; LA64-NEXT: and $a1, $a1, $a2
268-
; LA64-NEXT: sub.d $a0, $a0, $a1
269-
; LA64-NEXT: lu12i.w $a1, 209715
270-
; LA64-NEXT: ori $a1, $a1, 819
271-
; LA64-NEXT: and $a2, $a0, $a1
272-
; LA64-NEXT: srli.d $a0, $a0, 2
273-
; LA64-NEXT: and $a0, $a0, $a1
274-
; LA64-NEXT: add.d $a0, $a2, $a0
275-
; LA64-NEXT: srli.d $a1, $a0, 4
276-
; LA64-NEXT: add.d $a0, $a0, $a1
277-
; LA64-NEXT: lu12i.w $a1, 61680
278-
; LA64-NEXT: ori $a1, $a1, 3855
279-
; LA64-NEXT: and $a0, $a0, $a1
280-
; LA64-NEXT: lu12i.w $a1, 4112
281-
; LA64-NEXT: ori $a1, $a1, 257
282-
; LA64-NEXT: mul.d $a0, $a0, $a1
283-
; LA64-NEXT: bstrpick.d $a0, $a0, 31, 24
248+
; LA64-NEXT: bstrpick.d $a0, $a0, 31, 0
249+
; LA64-NEXT: vldi $vr0, 0
250+
; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
251+
; LA64-NEXT: vpcnt.d $vr0, $vr0
252+
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
284253
; LA64-NEXT: ret
285254
%1 = call i32 @llvm.ctpop.i32(i32 %a)
286255
ret i32 %1
@@ -327,30 +296,10 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
327296
;
328297
; LA64-LABEL: test_ctpop_i64:
329298
; LA64: # %bb.0:
330-
; LA64-NEXT: srli.d $a1, $a0, 1
331-
; LA64-NEXT: lu12i.w $a2, 349525
332-
; LA64-NEXT: ori $a2, $a2, 1365
333-
; LA64-NEXT: bstrins.d $a2, $a2, 62, 32
334-
; LA64-NEXT: and $a1, $a1, $a2
335-
; LA64-NEXT: sub.d $a0, $a0, $a1
336-
; LA64-NEXT: lu12i.w $a1, 209715
337-
; LA64-NEXT: ori $a1, $a1, 819
338-
; LA64-NEXT: bstrins.d $a1, $a1, 61, 32
339-
; LA64-NEXT: and $a2, $a0, $a1
340-
; LA64-NEXT: srli.d $a0, $a0, 2
341-
; LA64-NEXT: and $a0, $a0, $a1
342-
; LA64-NEXT: add.d $a0, $a2, $a0
343-
; LA64-NEXT: srli.d $a1, $a0, 4
344-
; LA64-NEXT: add.d $a0, $a0, $a1
345-
; LA64-NEXT: lu12i.w $a1, 61680
346-
; LA64-NEXT: ori $a1, $a1, 3855
347-
; LA64-NEXT: bstrins.d $a1, $a1, 59, 32
348-
; LA64-NEXT: and $a0, $a0, $a1
349-
; LA64-NEXT: lu12i.w $a1, 4112
350-
; LA64-NEXT: ori $a1, $a1, 257
351-
; LA64-NEXT: bstrins.d $a1, $a1, 56, 32
352-
; LA64-NEXT: mul.d $a0, $a0, $a1
353-
; LA64-NEXT: srli.d $a0, $a0, 56
299+
; LA64-NEXT: vldi $vr0, 0
300+
; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
301+
; LA64-NEXT: vpcnt.d $vr0, $vr0
302+
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
354303
; LA64-NEXT: ret
355304
%1 = call i64 @llvm.ctpop.i64(i64 %a)
356305
ret i64 %1

‎llvm/test/CodeGen/LoongArch/double-imm.ll

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -59,9 +59,7 @@ define double @f64_add_fimm1(double %a) nounwind {
5959
;
6060
; LA64-LABEL: f64_add_fimm1:
6161
; LA64: # %bb.0:
62-
; LA64-NEXT: addi.d $a0, $zero, 1
63-
; LA64-NEXT: movgr2fr.d $fa1, $a0
64-
; LA64-NEXT: ffint.d.l $fa1, $fa1
62+
; LA64-NEXT: vldi $vr1, -912
6563
; LA64-NEXT: fadd.d $fa0, $fa0, $fa1
6664
; LA64-NEXT: ret
6765
%1 = fadd double %a, 1.0
@@ -79,9 +77,7 @@ define double @f64_positive_fimm1() nounwind {
7977
;
8078
; LA64-LABEL: f64_positive_fimm1:
8179
; LA64: # %bb.0:
82-
; LA64-NEXT: addi.d $a0, $zero, 1
83-
; LA64-NEXT: movgr2fr.d $fa0, $a0
84-
; LA64-NEXT: ffint.d.l $fa0, $fa0
80+
; LA64-NEXT: vldi $vr0, -912
8581
; LA64-NEXT: ret
8682
ret double 1.0
8783
}

‎llvm/test/CodeGen/LoongArch/frame.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,8 @@ define i32 @test() nounwind {
1212
; CHECK-NEXT: addi.d $sp, $sp, -32
1313
; CHECK-NEXT: st.d $ra, $sp, 24 # 8-byte Folded Spill
1414
; CHECK-NEXT: st.w $zero, $sp, 16
15-
; CHECK-NEXT: st.d $zero, $sp, 8
16-
; CHECK-NEXT: st.d $zero, $sp, 0
15+
; CHECK-NEXT: vrepli.b $vr0, 0
16+
; CHECK-NEXT: vst $vr0, $sp, 0
1717
; CHECK-NEXT: addi.d $a0, $sp, 4
1818
; CHECK-NEXT: bl %plt(test1)
1919
; CHECK-NEXT: move $a0, $zero

‎llvm/test/CodeGen/LoongArch/get-setcc-result-type.ll

Lines changed: 3 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -5,22 +5,9 @@
55
define void @getSetCCResultType(ptr %p) {
66
; CHECK-LABEL: getSetCCResultType:
77
; CHECK: # %bb.0: # %entry
8-
; CHECK-NEXT: ld.w $a1, $a0, 0
9-
; CHECK-NEXT: ld.w $a2, $a0, 12
10-
; CHECK-NEXT: ld.w $a3, $a0, 4
11-
; CHECK-NEXT: ld.w $a4, $a0, 8
12-
; CHECK-NEXT: sltui $a1, $a1, 1
13-
; CHECK-NEXT: sub.d $a1, $zero, $a1
14-
; CHECK-NEXT: sltui $a3, $a3, 1
15-
; CHECK-NEXT: sub.d $a3, $zero, $a3
16-
; CHECK-NEXT: sltui $a4, $a4, 1
17-
; CHECK-NEXT: sub.d $a4, $zero, $a4
18-
; CHECK-NEXT: sltui $a2, $a2, 1
19-
; CHECK-NEXT: sub.d $a2, $zero, $a2
20-
; CHECK-NEXT: st.w $a2, $a0, 12
21-
; CHECK-NEXT: st.w $a4, $a0, 8
22-
; CHECK-NEXT: st.w $a3, $a0, 4
23-
; CHECK-NEXT: st.w $a1, $a0, 0
8+
; CHECK-NEXT: vld $vr0, $a0, 0
9+
; CHECK-NEXT: vseqi.w $vr0, $vr0, 0
10+
; CHECK-NEXT: vst $vr0, $a0, 0
2411
; CHECK-NEXT: ret
2512
entry:
2613
%0 = load <4 x i32>, ptr %p, align 16

‎llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s
1+
; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,LA32
22
; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
33

44
define void @constraint_l() {
@@ -32,9 +32,9 @@ define void @constraint_K() {
3232
}
3333

3434
define void @constraint_f() nounwind {
35-
; CHECK: error: couldn't allocate input reg for constraint 'f'
35+
; LA32: error: couldn't allocate input reg for constraint 'f'
3636
tail call void asm "fadd.s $$fa0, $$fa0, $0", "f"(float 0.0)
37-
; CHECK: error: couldn't allocate input reg for constraint 'f'
37+
; LA32: error: couldn't allocate input reg for constraint 'f'
3838
tail call void asm "fadd.s $$fa0, $$fa0, $0", "f"(double 0.0)
3939
ret void
4040
}

‎llvm/test/CodeGen/LoongArch/intrinsic-error.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s
1+
; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,LA32
22
; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
33

44
declare void @llvm.loongarch.dbar(i32)
@@ -54,7 +54,7 @@ entry:
5454
}
5555

5656
define void @movgr2fcsr(i32 %a) nounwind {
57-
; CHECK: llvm.loongarch.movgr2fcsr: requires basic 'f' target feature.
57+
; LA32: llvm.loongarch.movgr2fcsr: requires basic 'f' target feature.
5858
entry:
5959
call void @llvm.loongarch.movgr2fcsr(i32 1, i32 %a)
6060
ret void
@@ -75,7 +75,7 @@ entry:
7575
}
7676

7777
define i32 @movfcsr2gr() nounwind {
78-
; CHECK: llvm.loongarch.movfcsr2gr: requires basic 'f' target feature.
78+
; LA32: llvm.loongarch.movfcsr2gr: requires basic 'f' target feature.
7979
entry:
8080
%res = call i32 @llvm.loongarch.movfcsr2gr(i32 1)
8181
ret i32 %res

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