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[AMDGPU] Remove support for some old HSA COV2 asm directives
Namely, .hsa_code_object_version and .hsa_code_object_isa. I left .amdgpu_hsa_kernel in as it still is getting emitted on mesa3d.
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5 files changed

+2
-234
lines changed

5 files changed

+2
-234
lines changed

‎llvm/include/llvm/Support/AMDGPUMetadata.h

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,6 @@ namespace AMDGPU {
2929
//===----------------------------------------------------------------------===//
3030
namespace HSAMD {
3131

32-
/// HSA metadata major version for code object V2.
33-
constexpr uint32_t VersionMajorV2 = 1;
34-
/// HSA metadata minor version for code object V2.
35-
constexpr uint32_t VersionMinorV2 = 0;
36-
3732
/// HSA metadata major version for code object V3.
3833
constexpr uint32_t VersionMajorV3 = 1;
3934
/// HSA metadata minor version for code object V3.
@@ -49,10 +44,9 @@ constexpr uint32_t VersionMajorV5 = 1;
4944
/// HSA metadata minor version for code object V5.
5045
constexpr uint32_t VersionMinorV5 = 2;
5146

52-
/// HSA metadata beginning assembler directive.
47+
/// Old HSA metadata beginning assembler directive for V2. This is only used for
48+
/// diagnostics now.
5349
constexpr char AssemblerDirectiveBegin[] = ".amd_amdgpu_hsa_metadata";
54-
/// HSA metadata ending assembler directive.
55-
constexpr char AssemblerDirectiveEnd[] = ".end_amd_amdgpu_hsa_metadata";
5650

5751
/// Access qualifiers.
5852
enum class AccessQualifier : uint8_t {

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 0 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -1296,9 +1296,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
12961296
unsigned &VGPRBlocks, unsigned &SGPRBlocks);
12971297
bool ParseDirectiveAMDGCNTarget();
12981298
bool ParseDirectiveAMDHSAKernel();
1299-
bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);
1300-
bool ParseDirectiveHSACodeObjectVersion();
1301-
bool ParseDirectiveHSACodeObjectISA();
13021299
bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
13031300
bool ParseDirectiveAMDKernelCodeT();
13041301
// TODO: Possibly make subtargetHasRegister const.
@@ -5057,20 +5054,6 @@ bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {
50575054
return false;
50585055
}
50595056

5060-
bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,
5061-
uint32_t &Minor) {
5062-
if (ParseAsAbsoluteExpression(Major))
5063-
return TokError("invalid major version");
5064-
5065-
if (!trySkipToken(AsmToken::Comma))
5066-
return TokError("minor version number required, comma expected");
5067-
5068-
if (ParseAsAbsoluteExpression(Minor))
5069-
return TokError("invalid minor version");
5070-
5071-
return false;
5072-
}
5073-
50745057
bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
50755058
if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
50765059
return TokError("directive only supported for amdgcn architecture");
@@ -5542,60 +5525,6 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
55425525
return false;
55435526
}
55445527

5545-
bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {
5546-
uint32_t Major;
5547-
uint32_t Minor;
5548-
5549-
if (ParseDirectiveMajorMinor(Major, Minor))
5550-
return true;
5551-
5552-
getTargetStreamer().EmitDirectiveHSACodeObjectVersion(Major, Minor);
5553-
return false;
5554-
}
5555-
5556-
bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
5557-
uint32_t Major;
5558-
uint32_t Minor;
5559-
uint32_t Stepping;
5560-
StringRef VendorName;
5561-
StringRef ArchName;
5562-
5563-
// If this directive has no arguments, then use the ISA version for the
5564-
// targeted GPU.
5565-
if (isToken(AsmToken::EndOfStatement)) {
5566-
AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
5567-
getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(ISA.Major, ISA.Minor,
5568-
ISA.Stepping,
5569-
"AMD", "AMDGPU");
5570-
return false;
5571-
}
5572-
5573-
if (ParseDirectiveMajorMinor(Major, Minor))
5574-
return true;
5575-
5576-
if (!trySkipToken(AsmToken::Comma))
5577-
return TokError("stepping version number required, comma expected");
5578-
5579-
if (ParseAsAbsoluteExpression(Stepping))
5580-
return TokError("invalid stepping version");
5581-
5582-
if (!trySkipToken(AsmToken::Comma))
5583-
return TokError("vendor name required, comma expected");
5584-
5585-
if (!parseString(VendorName, "invalid vendor name"))
5586-
return true;
5587-
5588-
if (!trySkipToken(AsmToken::Comma))
5589-
return TokError("arch name required, comma expected");
5590-
5591-
if (!parseString(ArchName, "invalid arch name"))
5592-
return true;
5593-
5594-
getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(Major, Minor, Stepping,
5595-
VendorName, ArchName);
5596-
return false;
5597-
}
5598-
55995528
bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
56005529
amd_kernel_code_t &Header) {
56015530
// max_scratch_backing_memory_byte_size is deprecated. Ignore it while parsing
@@ -5883,12 +5812,6 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
58835812
if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin)
58845813
return ParseDirectiveHSAMetadata();
58855814
} else {
5886-
if (IDVal == ".hsa_code_object_version")
5887-
return ParseDirectiveHSACodeObjectVersion();
5888-
5889-
if (IDVal == ".hsa_code_object_isa")
5890-
return ParseDirectiveHSACodeObjectISA();
5891-
58925815
if (IDVal == ".amd_kernel_code_t")
58935816
return ParseDirectiveAMDKernelCodeT();
58945817

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

Lines changed: 0 additions & 112 deletions
Original file line numberDiff line numberDiff line change
@@ -35,27 +35,6 @@ using namespace llvm::AMDGPU;
3535
// AMDGPUTargetStreamer
3636
//===----------------------------------------------------------------------===//
3737

38-
static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor,
39-
uint32_t &Stepping, bool Sramecc, bool Xnack) {
40-
if (Major == 9 && Minor == 0) {
41-
switch (Stepping) {
42-
case 0:
43-
case 2:
44-
case 4:
45-
case 6:
46-
if (Xnack)
47-
Stepping++;
48-
}
49-
}
50-
}
51-
52-
bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) {
53-
HSAMD::Metadata HSAMetadata;
54-
if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
55-
return false;
56-
return EmitHSAMetadata(HSAMetadata);
57-
}
58-
5938
bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) {
6039
msgpack::Document HSAMetadataDoc;
6140
if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
@@ -238,23 +217,6 @@ void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() {
238217
OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n";
239218
}
240219

241-
void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion(
242-
uint32_t Major, uint32_t Minor) {
243-
OS << "\t.hsa_code_object_version " <<
244-
Twine(Major) << "," << Twine(Minor) << '\n';
245-
}
246-
247-
void
248-
AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major,
249-
uint32_t Minor,
250-
uint32_t Stepping,
251-
StringRef VendorName,
252-
StringRef ArchName) {
253-
convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
254-
OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << ","
255-
<< Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
256-
}
257-
258220
void
259221
AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
260222
OS << "\t.amd_kernel_code_t\n";
@@ -283,18 +245,6 @@ bool AMDGPUTargetAsmStreamer::EmitISAVersion() {
283245
return true;
284246
}
285247

286-
bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
287-
const AMDGPU::HSAMD::Metadata &HSAMetadata) {
288-
std::string HSAMetadataString;
289-
if (HSAMD::toString(HSAMetadata, HSAMetadataString))
290-
return false;
291-
292-
OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n';
293-
OS << HSAMetadataString << '\n';
294-
OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n';
295-
return true;
296-
}
297-
298248
bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
299249
msgpack::Document &HSAMetadataDoc, bool Strict) {
300250
HSAMD::V3::MetadataVerifier Verifier(Strict);
@@ -699,44 +649,6 @@ unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
699649

700650
void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {}
701651

702-
void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion(
703-
uint32_t Major, uint32_t Minor) {
704-
705-
EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()),
706-
ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) {
707-
OS.emitInt32(Major);
708-
OS.emitInt32(Minor);
709-
});
710-
}
711-
712-
void
713-
AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major,
714-
uint32_t Minor,
715-
uint32_t Stepping,
716-
StringRef VendorName,
717-
StringRef ArchName) {
718-
uint16_t VendorNameSize = VendorName.size() + 1;
719-
uint16_t ArchNameSize = ArchName.size() + 1;
720-
721-
unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
722-
sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
723-
VendorNameSize + ArchNameSize;
724-
725-
convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
726-
EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()),
727-
ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) {
728-
OS.emitInt16(VendorNameSize);
729-
OS.emitInt16(ArchNameSize);
730-
OS.emitInt32(Major);
731-
OS.emitInt32(Minor);
732-
OS.emitInt32(Stepping);
733-
OS.emitBytes(VendorName);
734-
OS.emitInt8(0); // NULL terminate VendorName
735-
OS.emitBytes(ArchName);
736-
OS.emitInt8(0); // NULL terminate ArchName
737-
});
738-
}
739-
740652
void
741653
AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
742654

@@ -818,30 +730,6 @@ bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
818730
return true;
819731
}
820732

821-
bool AMDGPUTargetELFStreamer::EmitHSAMetadata(
822-
const AMDGPU::HSAMD::Metadata &HSAMetadata) {
823-
std::string HSAMetadataString;
824-
if (HSAMD::toString(HSAMetadata, HSAMetadataString))
825-
return false;
826-
827-
// Create two labels to mark the beginning and end of the desc field
828-
// and a MCExpr to calculate the size of the desc field.
829-
auto &Context = getContext();
830-
auto *DescBegin = Context.createTempSymbol();
831-
auto *DescEnd = Context.createTempSymbol();
832-
auto *DescSZ = MCBinaryExpr::createSub(
833-
MCSymbolRefExpr::create(DescEnd, Context),
834-
MCSymbolRefExpr::create(DescBegin, Context), Context);
835-
836-
EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA,
837-
[&](MCELFStreamer &OS) {
838-
OS.emitLabel(DescBegin);
839-
OS.emitBytes(HSAMetadataString);
840-
OS.emitLabel(DescEnd);
841-
});
842-
return true;
843-
}
844-
845733
bool AMDGPUTargetAsmStreamer::EmitKernargPreloadHeader(
846734
const MCSubtargetInfo &STI) {
847735
for (int i = 0; i < 64; ++i) {

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h

Lines changed: 0 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -47,14 +47,6 @@ class AMDGPUTargetStreamer : public MCTargetStreamer {
4747

4848
virtual void EmitDirectiveAMDGCNTarget(){};
4949

50-
virtual void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
51-
uint32_t Minor){};
52-
53-
virtual void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor,
54-
uint32_t Stepping,
55-
StringRef VendorName,
56-
StringRef ArchName){};
57-
5850
virtual void EmitAMDKernelCodeT(const amd_kernel_code_t &Header){};
5951

6052
virtual void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type){};
@@ -65,9 +57,6 @@ class AMDGPUTargetStreamer : public MCTargetStreamer {
6557
/// \returns True on success, false on failure.
6658
virtual bool EmitISAVersion() { return true; }
6759

68-
/// \returns True on success, false on failure.
69-
virtual bool EmitHSAMetadataV2(StringRef HSAMetadataString);
70-
7160
/// \returns True on success, false on failure.
7261
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString);
7362

@@ -134,13 +123,6 @@ class AMDGPUTargetAsmStreamer final : public AMDGPUTargetStreamer {
134123

135124
void EmitDirectiveAMDGCNTarget() override;
136125

137-
void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
138-
uint32_t Minor) override;
139-
140-
void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor,
141-
uint32_t Stepping, StringRef VendorName,
142-
StringRef ArchName) override;
143-
144126
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
145127

146128
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override;
@@ -153,9 +135,6 @@ class AMDGPUTargetAsmStreamer final : public AMDGPUTargetStreamer {
153135
/// \returns True on success, false on failure.
154136
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override;
155137

156-
/// \returns True on success, false on failure.
157-
bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
158-
159138
/// \returns True on success, false on failure.
160139
bool EmitCodeEnd(const MCSubtargetInfo &STI) override;
161140

@@ -198,13 +177,6 @@ class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer {
198177

199178
void EmitDirectiveAMDGCNTarget() override;
200179

201-
void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
202-
uint32_t Minor) override;
203-
204-
void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor,
205-
uint32_t Stepping, StringRef VendorName,
206-
StringRef ArchName) override;
207-
208180
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
209181

210182
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override;
@@ -217,9 +189,6 @@ class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer {
217189
/// \returns True on success, false on failure.
218190
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override;
219191

220-
/// \returns True on success, false on failure.
221-
bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
222-
223192
/// \returns True on success, false on failure.
224193
bool EmitCodeEnd(const MCSubtargetInfo &STI) override;
225194

‎llvm/test/MC/AMDGPU/hsa_isa_version_attrs.s

Lines changed: 0 additions & 6 deletions
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