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[RISCV][GISel] Resolve CHECK prefix conflict and add a bunch of FIXMEs to bitmanip tests. NFC
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6 files changed

+107
-16
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6 files changed

+107
-16
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‎llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll

Lines changed: 33 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,9 @@
22
; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \
33
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I
44
; RUN: llc -mtriple=riscv32 -global-isel -mattr=+zbb -verify-machineinstrs < %s \
5-
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB-ZBKB
5+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB-ZBKB,RV32ZBB
66
; RUN: llc -mtriple=riscv32 -global-isel -mattr=+zbkb -verify-machineinstrs < %s \
7-
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB-ZBKB
7+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB-ZBKB,RV32ZBKB
88

99
define i32 @andn_i32(i32 %a, i32 %b) nounwind {
1010
; RV32I-LABEL: andn_i32:
@@ -334,21 +334,33 @@ define i8 @srli_i8(i8 %a) nounwind {
334334
ret i8 %1
335335
}
336336

337-
; We could use sext.b+srai, but slli+srai offers more opportunities for
338-
; comppressed instructions.
337+
; FIXME: We should use slli+srai with Zbb for better compression.
338+
; FIXME: We should combine back to back srai.
339339
define i8 @srai_i8(i8 %a) nounwind {
340340
; RV32I-LABEL: srai_i8:
341341
; RV32I: # %bb.0:
342342
; RV32I-NEXT: slli a0, a0, 24
343343
; RV32I-NEXT: srai a0, a0, 24
344344
; RV32I-NEXT: srai a0, a0, 5
345345
; RV32I-NEXT: ret
346+
;
347+
; RV32ZBB-LABEL: srai_i8:
348+
; RV32ZBB: # %bb.0:
349+
; RV32ZBB-NEXT: sext.b a0, a0
350+
; RV32ZBB-NEXT: srai a0, a0, 5
351+
; RV32ZBB-NEXT: ret
352+
;
353+
; RV32ZBKB-LABEL: srai_i8:
354+
; RV32ZBKB: # %bb.0:
355+
; RV32ZBKB-NEXT: slli a0, a0, 24
356+
; RV32ZBKB-NEXT: srai a0, a0, 24
357+
; RV32ZBKB-NEXT: srai a0, a0, 5
358+
; RV32ZBKB-NEXT: ret
346359
%1 = ashr i8 %a, 5
347360
ret i8 %1
348361
}
349362

350-
; We could use zext.h+srli, but slli+srli offers more opportunities for
351-
; comppressed instructions.
363+
; FIXME: We should use slli+srli.
352364
define i16 @srli_i16(i16 %a) nounwind {
353365
; RV32I-LABEL: srli_i16:
354366
; RV32I: # %bb.0:
@@ -367,15 +379,28 @@ define i16 @srli_i16(i16 %a) nounwind {
367379
ret i16 %1
368380
}
369381

370-
; We could use sext.h+srai, but slli+srai offers more opportunities for
371-
; comppressed instructions.
382+
; FIXME: We should use slli+srai with Zbb/Zbkb for better compression.
383+
; FIXME: We should combine back to back sraiw.
372384
define i16 @srai_i16(i16 %a) nounwind {
373385
; RV32I-LABEL: srai_i16:
374386
; RV32I: # %bb.0:
375387
; RV32I-NEXT: slli a0, a0, 16
376388
; RV32I-NEXT: srai a0, a0, 16
377389
; RV32I-NEXT: srai a0, a0, 9
378390
; RV32I-NEXT: ret
391+
;
392+
; RV32ZBB-LABEL: srai_i16:
393+
; RV32ZBB: # %bb.0:
394+
; RV32ZBB-NEXT: sext.h a0, a0
395+
; RV32ZBB-NEXT: srai a0, a0, 9
396+
; RV32ZBB-NEXT: ret
397+
;
398+
; RV32ZBKB-LABEL: srai_i16:
399+
; RV32ZBKB: # %bb.0:
400+
; RV32ZBKB-NEXT: slli a0, a0, 16
401+
; RV32ZBKB-NEXT: srai a0, a0, 16
402+
; RV32ZBKB-NEXT: srai a0, a0, 9
403+
; RV32ZBKB-NEXT: ret
379404
%1 = ashr i16 %a, 9
380405
ret i16 %1
381406
}

‎llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -616,6 +616,7 @@ define i32 @sextb_i32(i32 %a) nounwind {
616616
ret i32 %shr
617617
}
618618

619+
; FIXME: Combine back to back srai.
619620
define i64 @sextb_i64(i64 %a) nounwind {
620621
; RV32I-LABEL: sextb_i64:
621622
; RV32I: # %bb.0:
@@ -650,6 +651,7 @@ define i32 @sexth_i32(i32 %a) nounwind {
650651
ret i32 %shr
651652
}
652653

654+
; FIXME: Combine back to back srai.
653655
define i64 @sexth_i64(i64 %a) nounwind {
654656
; RV32I-LABEL: sexth_i64:
655657
; RV32I: # %bb.0:

‎llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,7 @@ define i64 @pack_i64_3(ptr %0, ptr %1) {
106106
ret i64 %8
107107
}
108108

109+
; FIXME: Use packh.
109110
define i32 @packh_i32(i32 %a, i32 %b) nounwind {
110111
; CHECK-LABEL: packh_i32:
111112
; CHECK: # %bb.0:
@@ -143,6 +144,7 @@ define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
143144
ret i32 %or
144145
}
145146

147+
; FIMXE: Use packh
146148
define i64 @packh_i64(i64 %a, i64 %b) nounwind {
147149
; CHECK-LABEL: packh_i64:
148150
; CHECK: # %bb.0:
@@ -161,6 +163,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
161163
ret i64 %or
162164
}
163165

166+
; FIXME The andi+srli for RV32ZBKB should fold to 0.
164167
define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
165168
; RV32I-LABEL: packh_i64_2:
166169
; RV32I: # %bb.0:

‎llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll

Lines changed: 51 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,10 +2,11 @@
22
; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
33
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I
44
; RUN: llc -mtriple=riscv64 -global-isel -mattr=+zbb -verify-machineinstrs < %s \
5-
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBB-ZBKB
5+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBB-ZBKB,RV64ZBB
66
; RUN: llc -mtriple=riscv64 -global-isel -mattr=+zbkb -verify-machineinstrs < %s \
7-
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBB-ZBKB
7+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBB-ZBKB,RV64ZBKB
88

9+
; FIXME: sext.w is unneeded.
910
define signext i32 @andn_i32(i32 signext %a, i32 signext %b) nounwind {
1011
; RV64I-LABEL: andn_i32:
1112
; RV64I: # %bb.0:
@@ -40,6 +41,7 @@ define i64 @andn_i64(i64 %a, i64 %b) nounwind {
4041
ret i64 %and
4142
}
4243

44+
; FIXME: sext.w is unneeded.
4345
define signext i32 @orn_i32(i32 signext %a, i32 signext %b) nounwind {
4446
; RV64I-LABEL: orn_i32:
4547
; RV64I: # %bb.0:
@@ -74,6 +76,7 @@ define i64 @orn_i64(i64 %a, i64 %b) nounwind {
7476
ret i64 %or
7577
}
7678

79+
; FIXME: sext.w is unneeded.
7780
define signext i32 @xnor_i32(i32 signext %a, i32 signext %b) nounwind {
7881
; RV64I-LABEL: xnor_i32:
7982
; RV64I: # %bb.0:
@@ -424,6 +427,7 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
424427
ret i64 %1
425428
}
426429

430+
; FIXME: We should use srli instead of srliw for better compression.
427431
define i8 @srli_i8(i8 %a) nounwind {
428432
; CHECK-LABEL: srli_i8:
429433
; CHECK: # %bb.0:
@@ -434,21 +438,33 @@ define i8 @srli_i8(i8 %a) nounwind {
434438
ret i8 %1
435439
}
436440

437-
; We could use sext.b+srai, but slli+srai offers more opportunities for
438-
; comppressed instructions.
441+
; FIXME: We should use slli+srai with Zbb for better compression.
442+
; FIXME: We should combine back to back sraiw.
439443
define i8 @srai_i8(i8 %a) nounwind {
440444
; RV64I-LABEL: srai_i8:
441445
; RV64I: # %bb.0:
442446
; RV64I-NEXT: slli a0, a0, 24
443447
; RV64I-NEXT: sraiw a0, a0, 24
444448
; RV64I-NEXT: sraiw a0, a0, 5
445449
; RV64I-NEXT: ret
450+
;
451+
; RV64ZBB-LABEL: srai_i8:
452+
; RV64ZBB: # %bb.0:
453+
; RV64ZBB-NEXT: sext.b a0, a0
454+
; RV64ZBB-NEXT: sraiw a0, a0, 5
455+
; RV64ZBB-NEXT: ret
456+
;
457+
; RV64ZBKB-LABEL: srai_i8:
458+
; RV64ZBKB: # %bb.0:
459+
; RV64ZBKB-NEXT: slli a0, a0, 24
460+
; RV64ZBKB-NEXT: sraiw a0, a0, 24
461+
; RV64ZBKB-NEXT: sraiw a0, a0, 5
462+
; RV64ZBKB-NEXT: ret
446463
%1 = ashr i8 %a, 5
447464
ret i8 %1
448465
}
449466

450-
; We could use zext.h+srli, but slli+srli offers more opportunities for
451-
; comppressed instructions.
467+
; FIXME: We should use slli+srli.
452468
define i16 @srli_i16(i16 %a) nounwind {
453469
; RV64I-LABEL: srli_i16:
454470
; RV64I: # %bb.0:
@@ -457,19 +473,46 @@ define i16 @srli_i16(i16 %a) nounwind {
457473
; RV64I-NEXT: and a0, a0, a1
458474
; RV64I-NEXT: srliw a0, a0, 6
459475
; RV64I-NEXT: ret
476+
;
477+
; RV64ZBB-LABEL: srli_i16:
478+
; RV64ZBB: # %bb.0:
479+
; RV64ZBB-NEXT: zext.h a0, a0
480+
; RV64ZBB-NEXT: srliw a0, a0, 6
481+
; RV64ZBB-NEXT: ret
482+
;
483+
; RV64ZBKB-LABEL: srli_i16:
484+
; RV64ZBKB: # %bb.0:
485+
; RV64ZBKB-NEXT: lui a1, 16
486+
; RV64ZBKB-NEXT: addi a1, a1, -1
487+
; RV64ZBKB-NEXT: and a0, a0, a1
488+
; RV64ZBKB-NEXT: srliw a0, a0, 6
489+
; RV64ZBKB-NEXT: ret
460490
%1 = lshr i16 %a, 6
461491
ret i16 %1
462492
}
463493

464-
; We could use sext.h+srai, but slli+srai offers more opportunities for
465-
; comppressed instructions.
494+
; FIXME: We should use slli+srai with Zbb/Zbkb for better compression.
495+
; FIXME: We should combine back to back sraiw.
466496
define i16 @srai_i16(i16 %a) nounwind {
467497
; RV64I-LABEL: srai_i16:
468498
; RV64I: # %bb.0:
469499
; RV64I-NEXT: slli a0, a0, 16
470500
; RV64I-NEXT: sraiw a0, a0, 16
471501
; RV64I-NEXT: sraiw a0, a0, 9
472502
; RV64I-NEXT: ret
503+
;
504+
; RV64ZBB-LABEL: srai_i16:
505+
; RV64ZBB: # %bb.0:
506+
; RV64ZBB-NEXT: sext.h a0, a0
507+
; RV64ZBB-NEXT: sraiw a0, a0, 9
508+
; RV64ZBB-NEXT: ret
509+
;
510+
; RV64ZBKB-LABEL: srai_i16:
511+
; RV64ZBKB: # %bb.0:
512+
; RV64ZBKB-NEXT: slli a0, a0, 16
513+
; RV64ZBKB-NEXT: sraiw a0, a0, 16
514+
; RV64ZBKB-NEXT: sraiw a0, a0, 9
515+
; RV64ZBKB-NEXT: ret
473516
%1 = ashr i16 %a, 9
474517
ret i16 %1
475518
}

‎llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66

77
declare i32 @llvm.ctlz.i32(i32, i1)
88

9+
; FIXME: We don't need the shift pair before the beqz for RV64I.
910
define signext i32 @ctlz_i32(i32 signext %a) nounwind {
1011
; RV64I-LABEL: ctlz_i32:
1112
; RV64I: # %bb.0:
@@ -126,6 +127,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
126127
ret i32 %2
127128
}
128129

130+
; FIXME: We don't need the shift pair before the beqz for RV64I.
129131
define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
130132
; RV64I-LABEL: log2_ceil_i32:
131133
; RV64I: # %bb.0:
@@ -264,6 +266,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
264266
ret i32 %4
265267
}
266268

269+
; FIXME: We don't need the shift pair before the beqz for RV64I.
267270
define i32 @ctlz_lshr_i32(i32 signext %a) {
268271
; RV64I-LABEL: ctlz_lshr_i32:
269272
; RV64I: # %bb.0:
@@ -995,6 +998,8 @@ define i64 @max_i64(i64 %a, i64 %b) nounwind {
995998
ret i64 %cond
996999
}
9971000

1001+
; FIXME: We don't need the shift pairs. The inputs are sign extended, we can
1002+
; compare them directly.
9981003
define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind {
9991004
; RV64I-LABEL: minu_i32:
10001005
; RV64I: # %bb.0:
@@ -1041,6 +1046,8 @@ define i64 @minu_i64(i64 %a, i64 %b) nounwind {
10411046
ret i64 %cond
10421047
}
10431048

1049+
; FIXME: We don't need the shift pairs. The inputs are sign extended, we can
1050+
; compare them directly.
10441051
define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind {
10451052
; RV64I-LABEL: maxu_i32:
10461053
; RV64I: # %bb.0:

‎llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
; RUN: llc -mtriple=riscv64 -global-isel -mattr=+zbkb -verify-machineinstrs < %s \
55
; RUN: | FileCheck %s -check-prefix=RV64ZBKB
66

7+
; FIXME: Use packw
78
define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {
89
; RV64I-LABEL: pack_i32:
910
; RV64I: # %bb.0:
@@ -30,6 +31,7 @@ define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {
3031
ret i32 %or
3132
}
3233

34+
; FIXME: Use packw
3335
define signext i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind {
3436
; RV64I-LABEL: pack_i32_2:
3537
; RV64I: # %bb.0:
@@ -52,6 +54,7 @@ define signext i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind {
5254
}
5355

5456
; Test case where we don't have a sign_extend_inreg after the or.
57+
; FIXME: Use packw
5558
define signext i32 @pack_i32_3(i16 zeroext %0, i16 zeroext %1, i32 signext %2) {
5659
; RV64I-LABEL: pack_i32_3:
5760
; RV64I: # %bb.0:
@@ -93,6 +96,7 @@ define i64 @pack_i64(i64 %a, i64 %b) nounwind {
9396
ret i64 %or
9497
}
9598

99+
; FIXME: The slli+srli isn't needed with pack.
96100
define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind {
97101
; RV64I-LABEL: pack_i64_2:
98102
; RV64I: # %bb.0:
@@ -141,6 +145,7 @@ define i64 @pack_i64_3(ptr %0, ptr %1) {
141145
ret i64 %8
142146
}
143147

148+
; FIXME: Use packh
144149
define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
145150
; RV64I-LABEL: packh_i32:
146151
; RV64I: # %bb.0:
@@ -168,6 +173,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
168173
ret i32 %or
169174
}
170175

176+
; FIXME: Use packh
171177
define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
172178
; RV64I-LABEL: packh_i32_2:
173179
; RV64I: # %bb.0:
@@ -191,6 +197,7 @@ define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
191197
ret i32 %or
192198
}
193199

200+
; FIXME: Use packh
194201
define i64 @packh_i64(i64 %a, i64 %b) nounwind {
195202
; RV64I-LABEL: packh_i64:
196203
; RV64I: # %bb.0:
@@ -238,6 +245,7 @@ define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
238245
ret i64 %or
239246
}
240247

248+
; FIXME: Use packh
241249
define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {
242250
; RV64I-LABEL: packh_i16:
243251
; RV64I: # %bb.0:
@@ -261,6 +269,7 @@ define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {
261269
ret i16 %or
262270
}
263271

272+
; FIXME: Use packh
264273
define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
265274
; RV64I-LABEL: packh_i16_2:
266275
; RV64I: # %bb.0:
@@ -289,6 +298,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
289298
ret i16 %8
290299
}
291300

301+
; FIXME: Use packh
292302
define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
293303
; RV64I-LABEL: packh_i16_3:
294304
; RV64I: # %bb.0:
@@ -394,6 +404,7 @@ define i64 @pack_i64_imm() {
394404
ret i64 1157442765409226768 ; 0x0101010101010101
395405
}
396406

407+
; FIXME: Use zext.h
397408
define i32 @zexth_i32(i32 %a) nounwind {
398409
; RV64I-LABEL: zexth_i32:
399410
; RV64I: # %bb.0:

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