Skip to content

Commit 62c5de3

Browse files
committed
[RISCV] Fix a place that convert an immediate to MCRegister and back to immediate.
This dropped the upper 32 bits of the immediate, but I'm not sure it is ever non-zero.
1 parent 95361cf commit 62c5de3

File tree

1 file changed

+1
-1
lines changed

1 file changed

+1
-1
lines changed

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -172,7 +172,7 @@ void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
172172
const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
173173
MCRegister Link = MI.getOperand(0).getReg();
174174
MCRegister Dest = MI.getOperand(1).getReg();
175-
MCRegister Imm = MI.getOperand(2).getImm();
175+
int64_t Imm = MI.getOperand(2).getImm();
176176
Fixups.push_back(MCFixup::create(
177177
0, Expr, MCFixupKind(RISCV::fixup_riscv_tlsdesc_call), MI.getLoc()));
178178
MCInst Call =

0 commit comments

Comments
 (0)