@@ -339,20 +339,20 @@ llvm.func @arm_sme_vector_to_tile_vert(%tileslice : i32,
339
339
340
340
341
341
llvm.func @arm_sme_tile_slice_to_vector_horiz (%tileslice : i32 ,
342
- %nxv16i1 : vector <[16 ]xi1 >,
343
- %nxv8i1 : vector <[8 ]xi1 >,
344
- %nxv4i1 : vector <[4 ]xi1 >,
345
- %nxv2i1 : vector <[2 ]xi1 >,
346
- %nxv1i1 : vector <[1 ]xi1 >,
347
- %nxv16i8 : vector <[16 ]xi8 >,
348
- %nxv8i16 : vector <[8 ]xi16 >,
349
- %nxv4i32 : vector <[4 ]xi32 >,
350
- %nxv2i64 : vector <[2 ]xi64 >,
351
- %nxv1i128 : vector <[1 ]xi128 >,
352
- %nxv8f16 : vector <[8 ]xf16 >,
353
- %nxv8bf16 : vector <[8 ]xbf16 >,
354
- %nxv4f32 : vector <[4 ]xf32 >,
355
- %nxv2f64 : vector <[2 ]xf64 >) {
342
+ %nxv16i1 : vector <[16 ]xi1 >,
343
+ %nxv8i1 : vector <[8 ]xi1 >,
344
+ %nxv4i1 : vector <[4 ]xi1 >,
345
+ %nxv2i1 : vector <[2 ]xi1 >,
346
+ %nxv1i1 : vector <[1 ]xi1 >,
347
+ %nxv16i8 : vector <[16 ]xi8 >,
348
+ %nxv8i16 : vector <[8 ]xi16 >,
349
+ %nxv4i32 : vector <[4 ]xi32 >,
350
+ %nxv2i64 : vector <[2 ]xi64 >,
351
+ %nxv1i128 : vector <[1 ]xi128 >,
352
+ %nxv8f16 : vector <[8 ]xf16 >,
353
+ %nxv8bf16 : vector <[8 ]xbf16 >,
354
+ %nxv4f32 : vector <[4 ]xf32 >,
355
+ %nxv2f64 : vector <[2 ]xf64 >) {
356
356
%tile = llvm.mlir.constant (0 : index ) : i32
357
357
// CHECK: call <vscale x 16 x i8> @llvm.aarch64.sme.read.horiz.nxv16i8
358
358
%res0 = " arm_sme.intr.read.horiz" (%nxv16i8 , %nxv16i1 , %tile , %tileslice )
@@ -387,20 +387,20 @@ llvm.func @arm_sme_tile_slice_to_vector_horiz(%tileslice : i32,
387
387
// -----
388
388
389
389
llvm.func @arm_sme_tile_slice_to_vector_vert (%tileslice : i32 ,
390
- %nxv16i1 : vector <[16 ]xi1 >,
391
- %nxv8i1 : vector <[8 ]xi1 >,
392
- %nxv4i1 : vector <[4 ]xi1 >,
393
- %nxv2i1 : vector <[2 ]xi1 >,
394
- %nxv1i1 : vector <[1 ]xi1 >,
395
- %nxv16i8 : vector <[16 ]xi8 >,
396
- %nxv8i16 : vector <[8 ]xi16 >,
397
- %nxv4i32 : vector <[4 ]xi32 >,
398
- %nxv2i64 : vector <[2 ]xi64 >,
390
+ %nxv16i1 : vector <[16 ]xi1 >,
391
+ %nxv8i1 : vector <[8 ]xi1 >,
392
+ %nxv4i1 : vector <[4 ]xi1 >,
393
+ %nxv2i1 : vector <[2 ]xi1 >,
394
+ %nxv1i1 : vector <[1 ]xi1 >,
395
+ %nxv16i8 : vector <[16 ]xi8 >,
396
+ %nxv8i16 : vector <[8 ]xi16 >,
397
+ %nxv4i32 : vector <[4 ]xi32 >,
398
+ %nxv2i64 : vector <[2 ]xi64 >,
399
399
%nxv1i128 : vector <[1 ]xi128 >,
400
- %nxv8f16 : vector <[8 ]xf16 >,
400
+ %nxv8f16 : vector <[8 ]xf16 >,
401
401
%nxv8bf16 : vector <[8 ]xbf16 >,
402
- %nxv4f32 : vector <[4 ]xf32 >,
403
- %nxv2f64 : vector <[2 ]xf64 >) {
402
+ %nxv4f32 : vector <[4 ]xf32 >,
403
+ %nxv2f64 : vector <[2 ]xf64 >) {
404
404
%tile = llvm.mlir.constant (0 : index ) : i32
405
405
// CHECK: call <vscale x 16 x i8> @llvm.aarch64.sme.read.vert.nxv16i8
406
406
%res0 = " arm_sme.intr.read.vert" (%nxv16i8 , %nxv16i1 , %tile , %tileslice )
0 commit comments