Skip to content

Commit 6320105

Browse files
committed
[DAGCombiner] Move the transform from RISCVISelLowering
1 parent 9e71239 commit 6320105

File tree

2 files changed

+13
-17
lines changed

2 files changed

+13
-17
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4251,6 +4251,19 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
42514251
sd_match(N1, m_UMaxLike(m_Specific(A), m_Specific(B))))
42524252
return DAG.getNegative(DAG.getNode(ISD::ABDU, DL, VT, A, B), DL, VT);
42534253

4254+
// (sub x, (select (ult x, y), 0, y)) -> (umin x, (sub x, y))
4255+
auto LK = TLI.getTypeConversion(*DAG.getContext(), VT);
4256+
if ((LK.first == TargetLoweringBase::TypeLegal ||
4257+
LK.first == TargetLoweringBase::TypePromoteInteger) &&
4258+
TLI.isOperationLegal(ISD::UMIN, LK.second)) {
4259+
SDValue Y;
4260+
if (sd_match(N1, m_OneUse(m_Select(m_SetCC(m_Specific(N0), m_Value(Y),
4261+
m_SpecificCondCode(ISD::SETULT)),
4262+
m_Zero(), m_Deferred(Y)))))
4263+
return DAG.getNode(ISD::UMIN, DL, VT, N0,
4264+
DAG.getNode(ISD::SUB, DL, VT, N0, Y));
4265+
}
4266+
42544267
return SDValue();
42554268
}
42564269

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -14895,23 +14895,6 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
1489514895
if (SDValue V = combineSubShiftToOrcB(N, DAG, Subtarget))
1489614896
return V;
1489714897

14898-
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14899-
auto LK = TLI.getTypeConversion(*DAG.getContext(), VT);
14900-
if ((LK.first == TargetLoweringBase::TypeLegal ||
14901-
LK.first == TargetLoweringBase::TypePromoteInteger) &&
14902-
TLI.isOperationLegal(ISD::UMIN, LK.second)) {
14903-
// fold (sub x, (select (ult x, y), 0, y)) -> (umin x, (sub x, y))
14904-
using namespace llvm::SDPatternMatch;
14905-
SDValue Y;
14906-
if (sd_match(N1, m_OneUse(m_Select(m_SetCC(m_Specific(N0), m_Value(Y),
14907-
m_SpecificCondCode(ISD::SETULT)),
14908-
m_Zero(), m_Deferred(Y))))) {
14909-
SDLoc DL(N);
14910-
return DAG.getNode(ISD::UMIN, DL, VT, N0,
14911-
DAG.getNode(ISD::SUB, DL, VT, N0, Y));
14912-
}
14913-
}
14914-
1491514898
// fold (sub x, (select lhs, rhs, cc, 0, y)) ->
1491614899
// (select lhs, rhs, cc, x, (sub x, y))
1491714900
return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false, Subtarget);

0 commit comments

Comments
 (0)