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!fixup address latest comments, thanks!
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+4
-3
lines changed

2 files changed

+4
-3
lines changed

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12262,14 +12262,15 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
1226212262
case CC_Range: {
1226312263
const Value *RHS, *LHS, *MHS;
1226412264
ISD::CondCode CC;
12265-
if (I->Low == I->High || I->Kind == CC_And) {
12265+
if (I->Low == I->High) {
1226612266
// Check Cond == I->Low.
1226712267
CC = ISD::SETEQ;
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LHS = Cond;
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RHS=I->Low;
1227012270
MHS = nullptr;
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} else {
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// Check I->Low <= Cond <= I->High.
12273+
assert(I->Kind != CC_And && "CC_And must be handled above");
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CC = ISD::SETLE;
1227412275
LHS = I->Low;
1227512276
MHS = Cond;

llvm/lib/CodeGen/SwitchLoweringUtils.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -365,7 +365,7 @@ void SwitchCG::SwitchLowering::findBitTestClusters(CaseClusterVector &Clusters,
365365

366366
// Check if the clusters contain one checking for 0 and another one checking
367367
// for a power-of-2 constant with matching destinations. Those clusters can be
368-
// combined to a single ane with CC_And.
368+
// combined to a single one with CC_And.
369369
unsigned ZeroIdx = -1;
370370
for (const auto &[Idx, C] : enumerate(Clusters)) {
371371
if (C.Kind != CC_Range || C.Low != C.High)
@@ -391,7 +391,7 @@ void SwitchCG::SwitchLowering::findBitTestClusters(CaseClusterVector &Clusters,
391391
return;
392392

393393
APInt Pow2 = Clusters[Pow2Idx].Low->getValue();
394-
APInt NewC = (Pow2 + 1) * -1;
394+
APInt NewC = ~Pow2;
395395
Clusters[ZeroIdx].Low = ConstantInt::get(SI->getContext(), NewC);
396396
Clusters[ZeroIdx].High = ConstantInt::get(SI->getContext(), NewC);
397397
Clusters[ZeroIdx].Kind = CC_And;

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