@@ -324,7 +324,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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// If this redefinition is dead, we need to add a dummy unit live
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// range covering the def slot.
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- if (lv_-> RegisterDefIsDead (mi, interval.reg ))
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+ if (mi-> registerDefIsDead ( interval.reg , tri_ ))
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interval.addRange (LiveRange (RedefIndex, RedefIndex+1 , OldValNo));
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DOUT << " RESULT: " ;
@@ -399,7 +399,7 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
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// If it is not used after definition, it is considered dead at
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// the instruction defining it. Hence its interval is:
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// [defSlot(def), defSlot(def)+1)
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- if (lv_-> RegisterDefIsDead (mi, interval.reg )) {
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+ if (mi-> registerDefIsDead ( interval.reg , tri_ )) {
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DOUT << " dead" ;
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end = getDefIndex (start) + 1 ;
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goto exit;
@@ -410,11 +410,11 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
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// [defSlot(def), useSlot(kill)+1)
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while (++mi != MBB->end ()) {
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baseIndex += InstrSlots::NUM;
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- if (lv_-> KillsRegister (mi, interval.reg )) {
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+ if (mi-> killsRegister ( interval.reg , tri_ )) {
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DOUT << " killed" ;
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end = getUseIndex (baseIndex) + 1 ;
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goto exit;
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- } else if (lv_-> ModifiesRegister (mi, interval.reg )) {
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+ } else if (mi-> modifiesRegister ( interval.reg , tri_ )) {
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// Another instruction redefines the register before it is ever read.
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// Then the register is essentially dead at the instruction that defines
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// it. Hence its interval is:
@@ -459,8 +459,9 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
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handlePhysicalRegisterDef (MBB, MI, MIIdx, getOrCreateInterval (reg), CopyMI);
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// Def of a register also defines its sub-registers.
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for (const unsigned * AS = tri_->getSubRegisters (reg); *AS; ++AS)
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- // Avoid processing some defs more than once.
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- if (!MI->findRegisterDefOperand (*AS))
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+ // If MI also modifies the sub-register explicitly, avoid processing it
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+ // more than once. Do not pass in TRI here so it checks for exact match.
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+ if (!MI->modifiesRegister (*AS))
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handlePhysicalRegisterDef (MBB, MI, MIIdx, getOrCreateInterval (*AS), 0 );
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}
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}
@@ -477,11 +478,11 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
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unsigned start = baseIndex;
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unsigned end = start;
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while (mi != MBB->end ()) {
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- if (lv_-> KillsRegister (mi, interval.reg )) {
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+ if (mi-> killsRegister ( interval.reg , tri_ )) {
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DOUT << " killed" ;
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end = getUseIndex (baseIndex) + 1 ;
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goto exit;
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- } else if (lv_-> ModifiesRegister (mi, interval.reg )) {
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+ } else if (mi-> modifiesRegister ( interval.reg , tri_ )) {
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// Another instruction redefines the register before it is ever read.
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// Then the register is essentially dead at the instruction that defines
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// it. Hence its interval is:
@@ -842,9 +843,9 @@ void LiveIntervals::rewriteImplicitOps(const LiveInterval &li,
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if (!vrm.isReMaterialized (Reg))
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continue ;
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MachineInstr *ReMatMI = vrm.getReMaterializedMI (Reg);
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- int OpIdx = ReMatMI->findRegisterUseOperandIdx (li.reg );
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- if (OpIdx != - 1 )
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- ReMatMI-> getOperand (OpIdx). setReg (NewVReg);
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+ MachineOperand *UseMO = ReMatMI->findRegisterUseOperand (li.reg );
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+ if (UseMO )
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+ UseMO-> setReg (NewVReg);
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}
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}
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@@ -1605,7 +1606,7 @@ addIntervalsForSpills(const LiveInterval &li,
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LiveRange *LR = &LI->ranges [LI->ranges .size ()-1 ];
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unsigned LastUseIdx = getBaseIndex (LR->end );
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MachineInstr *LastUse = getInstructionFromIndex (LastUseIdx);
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- int UseIdx = LastUse->findRegisterUseOperandIdx (LI->reg );
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+ int UseIdx = LastUse->findRegisterUseOperandIdx (LI->reg , false );
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assert (UseIdx != -1 );
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if (LastUse->getOperand (UseIdx).isImplicit () ||
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LastUse->getDesc ().getOperandConstraint (UseIdx,TOI::TIED_TO) == -1 ){
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