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[RISCV] When VLEN is exactly known, prefer VLMAX encoding for vsetvli (#75412)
If we know the exact VLEN, then we can tell if the AVL for particular operation is equivalent to the vsetvli xN, zero, <vtype> encoding. Using this encoding is better than having to materialize an immediate in a register, but worse than being able to use the vsetivli zero, imm, <type> encoding.
1 parent d7aee33 commit 632f1c5

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4 files changed

+198
-107
lines changed

4 files changed

+198
-107
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 20 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2580,8 +2580,15 @@ static SDValue getAllOnesMask(MVT VecVT, SDValue VL, const SDLoc &DL,
25802580
return DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
25812581
}
25822582

2583-
static SDValue getVLOp(uint64_t NumElts, const SDLoc &DL, SelectionDAG &DAG,
2584-
const RISCVSubtarget &Subtarget) {
2583+
static SDValue getVLOp(uint64_t NumElts, MVT ContainerVT, const SDLoc &DL,
2584+
SelectionDAG &DAG, const RISCVSubtarget &Subtarget) {
2585+
// If we know the exact VLEN, our VL is exactly equal to VLMAX, and
2586+
// we can't encode the AVL as an immediate, use the VLMAX encoding.
2587+
const auto [MinVLMAX, MaxVLMAX] =
2588+
RISCVTargetLowering::computeVLMAXBounds(ContainerVT, Subtarget);
2589+
if (MinVLMAX == MaxVLMAX && NumElts == MinVLMAX && NumElts > 31)
2590+
return DAG.getRegister(RISCV::X0, Subtarget.getXLenVT());
2591+
25852592
return DAG.getConstant(NumElts, DL, Subtarget.getXLenVT());
25862593
}
25872594

@@ -2598,7 +2605,7 @@ static std::pair<SDValue, SDValue>
25982605
getDefaultVLOps(uint64_t NumElts, MVT ContainerVT, const SDLoc &DL,
25992606
SelectionDAG &DAG, const RISCVSubtarget &Subtarget) {
26002607
assert(ContainerVT.isScalableVector() && "Expecting scalable container type");
2601-
SDValue VL = getVLOp(NumElts, DL, DAG, Subtarget);
2608+
SDValue VL = getVLOp(NumElts, ContainerVT, DL, DAG, Subtarget);
26022609
SDValue Mask = getAllOnesMask(ContainerVT, VL, DL, DAG);
26032610
return {Mask, VL};
26042611
}
@@ -8650,7 +8657,8 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
86508657
MVT VT = Op->getSimpleValueType(0);
86518658
MVT ContainerVT = getContainerForFixedLengthVector(VT);
86528659

8653-
SDValue VL = getVLOp(VT.getVectorNumElements(), DL, DAG, Subtarget);
8660+
SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG,
8661+
Subtarget);
86548662
SDValue IntID = DAG.getTargetConstant(VlsegInts[NF - 2], DL, XLenVT);
86558663
auto *Load = cast<MemIntrinsicSDNode>(Op);
86568664
SmallVector<EVT, 9> ContainerVTs(NF, ContainerVT);
@@ -8785,7 +8793,8 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
87858793
MVT VT = Op->getOperand(2).getSimpleValueType();
87868794
MVT ContainerVT = getContainerForFixedLengthVector(VT);
87878795

8788-
SDValue VL = getVLOp(VT.getVectorNumElements(), DL, DAG, Subtarget);
8796+
SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG,
8797+
Subtarget);
87898798
SDValue IntID = DAG.getTargetConstant(VssegInts[NF - 2], DL, XLenVT);
87908799
SDValue Ptr = Op->getOperand(NF + 2);
87918800

@@ -9244,7 +9253,7 @@ SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
92449253
// Set the vector length to only the number of elements we care about. Note
92459254
// that for slideup this includes the offset.
92469255
unsigned EndIndex = OrigIdx + SubVecVT.getVectorNumElements();
9247-
SDValue VL = getVLOp(EndIndex, DL, DAG, Subtarget);
9256+
SDValue VL = getVLOp(EndIndex, ContainerVT, DL, DAG, Subtarget);
92489257

92499258
// Use tail agnostic policy if we're inserting over Vec's tail.
92509259
unsigned Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
@@ -9421,7 +9430,8 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
94219430
getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).first;
94229431
// Set the vector length to only the number of elements we care about. This
94239432
// avoids sliding down elements we're going to discard straight away.
9424-
SDValue VL = getVLOp(SubVecVT.getVectorNumElements(), DL, DAG, Subtarget);
9433+
SDValue VL = getVLOp(SubVecVT.getVectorNumElements(), ContainerVT, DL, DAG,
9434+
Subtarget);
94259435
SDValue SlidedownAmt = DAG.getConstant(OrigIdx, DL, XLenVT);
94269436
SDValue Slidedown =
94279437
getVSlidedown(DAG, Subtarget, DL, ContainerVT,
@@ -9828,7 +9838,7 @@ RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,
98289838
MVT XLenVT = Subtarget.getXLenVT();
98299839
MVT ContainerVT = getContainerForFixedLengthVector(VT);
98309840

9831-
SDValue VL = getVLOp(VT.getVectorNumElements(), DL, DAG, Subtarget);
9841+
SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG, Subtarget);
98329842

98339843
bool IsMaskOp = VT.getVectorElementType() == MVT::i1;
98349844
SDValue IntID = DAG.getTargetConstant(
@@ -9872,7 +9882,8 @@ RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
98729882

98739883
MVT ContainerVT = getContainerForFixedLengthVector(VT);
98749884

9875-
SDValue VL = getVLOp(VT.getVectorNumElements(), DL, DAG, Subtarget);
9885+
SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG,
9886+
Subtarget);
98769887

98779888
SDValue NewValue =
98789889
convertToScalableVector(ContainerVT, StoreVal, DAG, Subtarget);

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

Lines changed: 174 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -284,48 +284,76 @@ define void @extract_v8i32_nxv16i32_8(<vscale x 16 x i32> %x, ptr %y) {
284284
}
285285

286286
define void @extract_v8i1_v64i1_0(ptr %x, ptr %y) {
287-
; CHECK-LABEL: extract_v8i1_v64i1_0:
288-
; CHECK: # %bb.0:
289-
; CHECK-NEXT: li a2, 64
290-
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
291-
; CHECK-NEXT: vlm.v v8, (a0)
292-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
293-
; CHECK-NEXT: vsm.v v8, (a1)
294-
; CHECK-NEXT: ret
287+
; CHECK-V-LABEL: extract_v8i1_v64i1_0:
288+
; CHECK-V: # %bb.0:
289+
; CHECK-V-NEXT: li a2, 64
290+
; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
291+
; CHECK-V-NEXT: vlm.v v8, (a0)
292+
; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
293+
; CHECK-V-NEXT: vsm.v v8, (a1)
294+
; CHECK-V-NEXT: ret
295+
;
296+
; CHECK-KNOWNVLEN128-LABEL: extract_v8i1_v64i1_0:
297+
; CHECK-KNOWNVLEN128: # %bb.0:
298+
; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
299+
; CHECK-KNOWNVLEN128-NEXT: vlm.v v8, (a0)
300+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
301+
; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
302+
; CHECK-KNOWNVLEN128-NEXT: ret
295303
%a = load <64 x i1>, ptr %x
296304
%c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0)
297305
store <8 x i1> %c, ptr %y
298306
ret void
299307
}
300308

301309
define void @extract_v8i1_v64i1_8(ptr %x, ptr %y) {
302-
; CHECK-LABEL: extract_v8i1_v64i1_8:
303-
; CHECK: # %bb.0:
304-
; CHECK-NEXT: li a2, 64
305-
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
306-
; CHECK-NEXT: vlm.v v8, (a0)
307-
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
308-
; CHECK-NEXT: vslidedown.vi v8, v8, 1
309-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
310-
; CHECK-NEXT: vsm.v v8, (a1)
311-
; CHECK-NEXT: ret
310+
; CHECK-V-LABEL: extract_v8i1_v64i1_8:
311+
; CHECK-V: # %bb.0:
312+
; CHECK-V-NEXT: li a2, 64
313+
; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
314+
; CHECK-V-NEXT: vlm.v v8, (a0)
315+
; CHECK-V-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
316+
; CHECK-V-NEXT: vslidedown.vi v8, v8, 1
317+
; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
318+
; CHECK-V-NEXT: vsm.v v8, (a1)
319+
; CHECK-V-NEXT: ret
320+
;
321+
; CHECK-KNOWNVLEN128-LABEL: extract_v8i1_v64i1_8:
322+
; CHECK-KNOWNVLEN128: # %bb.0:
323+
; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
324+
; CHECK-KNOWNVLEN128-NEXT: vlm.v v8, (a0)
325+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
326+
; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 1
327+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
328+
; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
329+
; CHECK-KNOWNVLEN128-NEXT: ret
312330
%a = load <64 x i1>, ptr %x
313331
%c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8)
314332
store <8 x i1> %c, ptr %y
315333
ret void
316334
}
317335

318336
define void @extract_v8i1_v64i1_48(ptr %x, ptr %y) {
319-
; CHECK-LABEL: extract_v8i1_v64i1_48:
320-
; CHECK: # %bb.0:
321-
; CHECK-NEXT: li a2, 64
322-
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
323-
; CHECK-NEXT: vlm.v v8, (a0)
324-
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
325-
; CHECK-NEXT: vslidedown.vi v8, v8, 6
326-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
327-
; CHECK-NEXT: vsm.v v8, (a1)
328-
; CHECK-NEXT: ret
337+
; CHECK-V-LABEL: extract_v8i1_v64i1_48:
338+
; CHECK-V: # %bb.0:
339+
; CHECK-V-NEXT: li a2, 64
340+
; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
341+
; CHECK-V-NEXT: vlm.v v8, (a0)
342+
; CHECK-V-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
343+
; CHECK-V-NEXT: vslidedown.vi v8, v8, 6
344+
; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
345+
; CHECK-V-NEXT: vsm.v v8, (a1)
346+
; CHECK-V-NEXT: ret
347+
;
348+
; CHECK-KNOWNVLEN128-LABEL: extract_v8i1_v64i1_48:
349+
; CHECK-KNOWNVLEN128: # %bb.0:
350+
; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
351+
; CHECK-KNOWNVLEN128-NEXT: vlm.v v8, (a0)
352+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
353+
; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 6
354+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
355+
; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
356+
; CHECK-KNOWNVLEN128-NEXT: ret
329357
%a = load <64 x i1>, ptr %x
330358
%c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48)
331359
store <8 x i1> %c, ptr %y
@@ -407,79 +435,138 @@ define void @extract_v8i1_nxv64i1_192(<vscale x 64 x i1> %x, ptr %y) {
407435
}
408436

409437
define void @extract_v2i1_v64i1_0(ptr %x, ptr %y) {
410-
; CHECK-LABEL: extract_v2i1_v64i1_0:
411-
; CHECK: # %bb.0:
412-
; CHECK-NEXT: li a2, 64
413-
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
414-
; CHECK-NEXT: vlm.v v0, (a0)
415-
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
416-
; CHECK-NEXT: vmv.v.i v8, 0
417-
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
418-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
419-
; CHECK-NEXT: vmv.v.i v9, 0
420-
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
421-
; CHECK-NEXT: vmv.v.v v9, v8
422-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
423-
; CHECK-NEXT: vmsne.vi v8, v9, 0
424-
; CHECK-NEXT: vsm.v v8, (a1)
425-
; CHECK-NEXT: ret
438+
; CHECK-V-LABEL: extract_v2i1_v64i1_0:
439+
; CHECK-V: # %bb.0:
440+
; CHECK-V-NEXT: li a2, 64
441+
; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
442+
; CHECK-V-NEXT: vlm.v v0, (a0)
443+
; CHECK-V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
444+
; CHECK-V-NEXT: vmv.v.i v8, 0
445+
; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
446+
; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
447+
; CHECK-V-NEXT: vmv.v.i v9, 0
448+
; CHECK-V-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
449+
; CHECK-V-NEXT: vmv.v.v v9, v8
450+
; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
451+
; CHECK-V-NEXT: vmsne.vi v8, v9, 0
452+
; CHECK-V-NEXT: vsm.v v8, (a1)
453+
; CHECK-V-NEXT: ret
454+
;
455+
; CHECK-KNOWNVLEN128-LABEL: extract_v2i1_v64i1_0:
456+
; CHECK-KNOWNVLEN128: # %bb.0:
457+
; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
458+
; CHECK-KNOWNVLEN128-NEXT: vlm.v v0, (a0)
459+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
460+
; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
461+
; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
462+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
463+
; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v9, 0
464+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
465+
; CHECK-KNOWNVLEN128-NEXT: vmv.v.v v9, v8
466+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
467+
; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v8, v9, 0
468+
; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
469+
; CHECK-KNOWNVLEN128-NEXT: ret
426470
%a = load <64 x i1>, ptr %x
427471
%c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0)
428472
store <2 x i1> %c, ptr %y
429473
ret void
430474
}
431475

432476
define void @extract_v2i1_v64i1_2(ptr %x, ptr %y) {
433-
; CHECK-LABEL: extract_v2i1_v64i1_2:
434-
; CHECK: # %bb.0:
435-
; CHECK-NEXT: li a2, 64
436-
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
437-
; CHECK-NEXT: vlm.v v0, (a0)
438-
; CHECK-NEXT: vmv.v.i v8, 0
439-
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
440-
; CHECK-NEXT: vsetivli zero, 2, e8, m1, ta, ma
441-
; CHECK-NEXT: vslidedown.vi v8, v8, 2
442-
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
443-
; CHECK-NEXT: vmsne.vi v0, v8, 0
444-
; CHECK-NEXT: vmv.v.i v8, 0
445-
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
446-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
447-
; CHECK-NEXT: vmv.v.i v9, 0
448-
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
449-
; CHECK-NEXT: vmv.v.v v9, v8
450-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
451-
; CHECK-NEXT: vmsne.vi v8, v9, 0
452-
; CHECK-NEXT: vsm.v v8, (a1)
453-
; CHECK-NEXT: ret
477+
; CHECK-V-LABEL: extract_v2i1_v64i1_2:
478+
; CHECK-V: # %bb.0:
479+
; CHECK-V-NEXT: li a2, 64
480+
; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
481+
; CHECK-V-NEXT: vlm.v v0, (a0)
482+
; CHECK-V-NEXT: vmv.v.i v8, 0
483+
; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
484+
; CHECK-V-NEXT: vsetivli zero, 2, e8, m1, ta, ma
485+
; CHECK-V-NEXT: vslidedown.vi v8, v8, 2
486+
; CHECK-V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
487+
; CHECK-V-NEXT: vmsne.vi v0, v8, 0
488+
; CHECK-V-NEXT: vmv.v.i v8, 0
489+
; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
490+
; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
491+
; CHECK-V-NEXT: vmv.v.i v9, 0
492+
; CHECK-V-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
493+
; CHECK-V-NEXT: vmv.v.v v9, v8
494+
; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
495+
; CHECK-V-NEXT: vmsne.vi v8, v9, 0
496+
; CHECK-V-NEXT: vsm.v v8, (a1)
497+
; CHECK-V-NEXT: ret
498+
;
499+
; CHECK-KNOWNVLEN128-LABEL: extract_v2i1_v64i1_2:
500+
; CHECK-KNOWNVLEN128: # %bb.0:
501+
; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
502+
; CHECK-KNOWNVLEN128-NEXT: vlm.v v0, (a0)
503+
; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
504+
; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
505+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, m1, ta, ma
506+
; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 2
507+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
508+
; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v0, v8, 0
509+
; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
510+
; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
511+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
512+
; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v9, 0
513+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
514+
; CHECK-KNOWNVLEN128-NEXT: vmv.v.v v9, v8
515+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
516+
; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v8, v9, 0
517+
; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
518+
; CHECK-KNOWNVLEN128-NEXT: ret
454519
%a = load <64 x i1>, ptr %x
455520
%c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2)
456521
store <2 x i1> %c, ptr %y
457522
ret void
458523
}
459524

460525
define void @extract_v2i1_v64i1_42(ptr %x, ptr %y) {
461-
; CHECK-LABEL: extract_v2i1_v64i1_42:
462-
; CHECK: # %bb.0:
463-
; CHECK-NEXT: li a2, 64
464-
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
465-
; CHECK-NEXT: vlm.v v0, (a0)
466-
; CHECK-NEXT: vmv.v.i v8, 0
467-
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
468-
; CHECK-NEXT: li a0, 42
469-
; CHECK-NEXT: vsetivli zero, 2, e8, m4, ta, ma
470-
; CHECK-NEXT: vslidedown.vx v8, v8, a0
471-
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
472-
; CHECK-NEXT: vmsne.vi v0, v8, 0
473-
; CHECK-NEXT: vmv.v.i v8, 0
474-
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
475-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
476-
; CHECK-NEXT: vmv.v.i v9, 0
477-
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
478-
; CHECK-NEXT: vmv.v.v v9, v8
479-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
480-
; CHECK-NEXT: vmsne.vi v8, v9, 0
481-
; CHECK-NEXT: vsm.v v8, (a1)
482-
; CHECK-NEXT: ret
526+
; CHECK-V-LABEL: extract_v2i1_v64i1_42:
527+
; CHECK-V: # %bb.0:
528+
; CHECK-V-NEXT: li a2, 64
529+
; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
530+
; CHECK-V-NEXT: vlm.v v0, (a0)
531+
; CHECK-V-NEXT: vmv.v.i v8, 0
532+
; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
533+
; CHECK-V-NEXT: li a0, 42
534+
; CHECK-V-NEXT: vsetivli zero, 2, e8, m4, ta, ma
535+
; CHECK-V-NEXT: vslidedown.vx v8, v8, a0
536+
; CHECK-V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
537+
; CHECK-V-NEXT: vmsne.vi v0, v8, 0
538+
; CHECK-V-NEXT: vmv.v.i v8, 0
539+
; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
540+
; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
541+
; CHECK-V-NEXT: vmv.v.i v9, 0
542+
; CHECK-V-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
543+
; CHECK-V-NEXT: vmv.v.v v9, v8
544+
; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
545+
; CHECK-V-NEXT: vmsne.vi v8, v9, 0
546+
; CHECK-V-NEXT: vsm.v v8, (a1)
547+
; CHECK-V-NEXT: ret
548+
;
549+
; CHECK-KNOWNVLEN128-LABEL: extract_v2i1_v64i1_42:
550+
; CHECK-KNOWNVLEN128: # %bb.0:
551+
; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
552+
; CHECK-KNOWNVLEN128-NEXT: vlm.v v0, (a0)
553+
; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
554+
; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
555+
; CHECK-KNOWNVLEN128-NEXT: li a0, 42
556+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, m4, ta, ma
557+
; CHECK-KNOWNVLEN128-NEXT: vslidedown.vx v8, v8, a0
558+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
559+
; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v0, v8, 0
560+
; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
561+
; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
562+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
563+
; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v9, 0
564+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
565+
; CHECK-KNOWNVLEN128-NEXT: vmv.v.v v9, v8
566+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
567+
; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v8, v9, 0
568+
; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
569+
; CHECK-KNOWNVLEN128-NEXT: ret
483570
%a = load <64 x i1>, ptr %x
484571
%c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42)
485572
store <2 x i1> %c, ptr %y
@@ -660,6 +747,3 @@ declare <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %vec, i64 %i
660747

661748
declare <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
662749
declare <8 x i32> @llvm.vector.extract.v8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
663-
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
664-
; CHECK-KNOWNVLEN128: {{.*}}
665-
; CHECK-V: {{.*}}

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