[VPlan] Print flags for VPWidenCastRecipe.

Update VPWidenCastRecipe to also print flags. Simplify nneg printing
test and replace hard-coded value number references with patterns.

Author: fhahn

llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

@@ -802,6 +802,7 @@ void VPWidenCastRecipe::print(raw_ostream &O, const Twine &Indent,
   O << Indent << "WIDEN-CAST ";
   printAsOperand(O, SlotTracker);
   O << " = " << Instruction::getOpcodeName(Opcode) << " ";
+  printFlags(O);
   printOperands(O, SlotTracker);
   O << " to " << *getResultType();
 }

llvm/test/Transforms/LoopVectorize/vplan-printing.ll

@@ -809,23 +809,22 @@ exit:
 define void @zext_nneg(ptr noalias %p, ptr noalias %p1) {
 ; CHECK-LABEL: LV: Checking a loop in 'zext_nneg'
 ; CHECK:       VPlan 'Initial VPlan for VF={4},UF>=1' {
-; CHECK-NEXT:  Live-in vp<%0> = vector-trip-count
-; CHECK-NEXT:  Live-in ir<0> = original trip-count
+; CHECK-NEXT:  Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
+; CHECK-NEXT:  Live-in ir<1000> = original trip-count
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  vector.ph:
 ; CHECK-NEXT:  Successor(s): vector loop
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  <x1> vector loop: {
 ; CHECK-NEXT:  vector.body:
-; CHECK-NEXT:    EMIT vp<%1> = CANONICAL-INDUCTION ir<0>, vp<%8>
-; CHECK-NEXT:    vp<%2>    = DERIVED-IV ir<0> + vp<%1> * ir<1> (truncated to i32)
-; CHECK-NEXT:    vp<%3> = SCALAR-STEPS vp<%2>, ir<1>
-; CHECK-NEXT:    CLONE ir<%zext> = zext nneg vp<%3>
-; CHECK-NEXT:    CLONE ir<%idx2> = getelementptr ir<%p>, ir<%zext>
-; CHECK-NEXT:    WIDEN ir<%1> = load ir<%idx2>
-; CHECK-NEXT:    REPLICATE store ir<%1>, ir<%p1>
-; CHECK-NEXT:    EMIT vp<%8> = VF * UF + nuw vp<%1>
-; CHECK-NEXT:    EMIT branch-on-count vp<%8>, vp<%0>
+; CHECK-NEXT:    EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
+; CHECK-NEXT:    vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
+; CHECK-NEXT:    CLONE ir<%idx> = getelementptr ir<%p>, vp<[[STEPS]]>
+; CHECK-NEXT:    WIDEN ir<%l> = load ir<%idx>
+; CHECK-NEXT:    WIDEN-CAST ir<%zext> = zext nneg ir<%l>
+; CHECK-NEXT:    REPLICATE store ir<%zext>, ir<%p1>
+; CHECK-NEXT:    EMIT vp<[[CAN_IV_NEXT]]> = VF * UF + nuw vp<[[CAN_IV]]>
+; CHECK-NEXT:    EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>
 ; CHECK-NEXT:  No successors
 ; CHECK-NEXT: }
 ;
@@ -834,13 +833,12 @@ entry:
 
 body:
   %iv = phi i64 [ %next, %body ], [ 0, %entry ]
-  %0 = trunc i64 %iv to i32
-  %zext = zext nneg i32 %0 to i64
-  %idx2 = getelementptr double, ptr %p, i64 %zext
-  %1 = load double, ptr %idx2, align 8
-  store double %1, ptr %p1, align 8
+  %idx = getelementptr i32, ptr %p, i64 %iv
+  %l = load i32, ptr %idx, align 8
+  %zext = zext nneg i32 %l to i64
+  store i64 %zext, ptr %p1, align 8
   %next = add i64 %iv, 1
-  %cmp = icmp eq i64 %next, 0
+  %cmp = icmp eq i64 %next, 1000
   br i1 %cmp, label %exit, label %body
 
 exit: