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SpencerAbsonSpencerAbson
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[AArch64] Add assembly/disassembly for zeroing SVE2 integer instructions (#113473)
This patch adds assembly/disassembly for the following SVE2.2 instructions - SQABS (zeroing) - SQNEG (zeroing) - URECPE (zeroing) - USQRTE (zeroing) - Refactor the existing merging forms to remove the now redundant bit 17 argument. - In accordance with: https://developer.arm.com/documentation/ddi0602/latest/
1 parent 09160a9 commit 6414894

14 files changed

+366
-20
lines changed

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3586,10 +3586,10 @@ let Predicates = [HasSVE2orSME] in {
35863586
defm UMINP_ZPmZ : sve2_int_arith_pred<0b101111, "uminp", int_aarch64_sve_uminp>;
35873587

35883588
// SVE2 integer unary operations (predicated)
3589-
defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b000, "urecpe", int_aarch64_sve_urecpe>;
3590-
defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b001, "ursqrte", int_aarch64_sve_ursqrte>;
3591-
defm SQABS_ZPmZ : sve2_int_un_pred_arit<0b100, "sqabs", int_aarch64_sve_sqabs>;
3592-
defm SQNEG_ZPmZ : sve2_int_un_pred_arit<0b101, "sqneg", int_aarch64_sve_sqneg>;
3589+
defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b00, "urecpe", int_aarch64_sve_urecpe>;
3590+
defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b01, "ursqrte", int_aarch64_sve_ursqrte>;
3591+
defm SQABS_ZPmZ : sve2_int_un_pred_arit< 0b10, "sqabs", int_aarch64_sve_sqabs>;
3592+
defm SQNEG_ZPmZ : sve2_int_un_pred_arit< 0b11, "sqneg", int_aarch64_sve_sqneg>;
35933593

35943594
// SVE2 saturating add/subtract
35953595
defm SQADD_ZPmZ : sve2_int_arith_pred<0b110000, "sqadd", int_aarch64_sve_sqadd>;
@@ -4236,6 +4236,12 @@ let Predicates = [HasSVE2p2orSME2p2] in {
42364236
// Signed integer base 2 logarithm of fp value, zeroing predicate
42374237
defm FLOGB_ZPzZ : sve_fp_z2op_p_zd_d_flogb<"flogb">;
42384238

4239+
// SVE2 integer unary operations, zeroing predicate
4240+
def URECPE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b00, "urecpe", ZPR32>;
4241+
def URSQRTE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b01, "ursqrte", ZPR32>;
4242+
defm SQABS_ZPzZ : sve2_int_un_pred_arit_z<0b10, "sqabs">;
4243+
defm SQNEG_ZPzZ : sve2_int_un_pred_arit_z<0b11, "sqneg">;
4244+
42394245
// Floating point round to integral fp value in integer size range
42404246
// Merging
42414247
defm FRINT32Z_ZPmZ : sve_fp_2op_p_zd_frint<0b00, "frint32z">;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 40 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3964,7 +3964,7 @@ multiclass sve2_int_sadd_long_accum_pairwise<bit U, string asm, SDPatternOperato
39643964
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv4i32, !cast<Instruction>(NAME # _D)>;
39653965
}
39663966

3967-
class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
3967+
class sve2_int_un_pred_arit<bits<2> sz, bits<2> opc,
39683968
string asm, ZPRRegOp zprty>
39693969
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
39703970
asm, "\t$Zd, $Pg/m, $Zn",
@@ -3976,23 +3976,44 @@ class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
39763976
let Inst{31-24} = 0b01000100;
39773977
let Inst{23-22} = sz;
39783978
let Inst{21-20} = 0b00;
3979-
let Inst{19} = Q;
3980-
let Inst{18} = 0b0;
3981-
let Inst{17-16} = opc;
3979+
let Inst{19} = opc{1};
3980+
let Inst{18-17} = 0b00;
3981+
let Inst{16} = opc{0};
39823982
let Inst{15-13} = 0b101;
39833983
let Inst{12-10} = Pg;
39843984
let Inst{9-5} = Zn;
39853985
let Inst{4-0} = Zd;
3986-
39873986
let Constraints = "$Zd = $_Zd";
39883987
let DestructiveInstType = DestructiveUnaryPassthru;
39893988
let ElementSize = zprty.ElementSize;
39903989
let hasSideEffects = 0;
39913990
}
39923991

3993-
multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm,
3992+
class sve2_int_un_pred_arit_z<bits<2> sz, bits<2> opc,
3993+
string asm, ZPRRegOp zprty>
3994+
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
3995+
asm, "\t$Zd, $Pg/z, $Zn",
3996+
"",
3997+
[]>, Sched<[]> {
3998+
bits<3> Pg;
3999+
bits<5> Zd;
4000+
bits<5> Zn;
4001+
let Inst{31-24} = 0b01000100;
4002+
let Inst{23-22} = sz;
4003+
let Inst{21-20} = 0b00;
4004+
let Inst{19} = opc{1};
4005+
let Inst{18-17} = 0b01;
4006+
let Inst{16} = opc{0};
4007+
let Inst{15-13} = 0b101;
4008+
let Inst{12-10} = Pg;
4009+
let Inst{9-5} = Zn;
4010+
let Inst{4-0} = Zd;
4011+
let hasSideEffects = 0;
4012+
}
4013+
4014+
multiclass sve2_int_un_pred_arit_s<bits<2> opc, string asm,
39944015
SDPatternOperator op> {
3995-
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>,
4016+
def _S : sve2_int_un_pred_arit<0b10, opc, asm, ZPR32>,
39964017
SVEPseudo2Instr<NAME # _S, 1>;
39974018

39984019
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
@@ -4002,14 +4023,14 @@ multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm,
40024023
defm : SVE_3_Op_Undef_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Pseudo>(NAME # _S_UNDEF)>;
40034024
}
40044025

4005-
multiclass sve2_int_un_pred_arit<bits<3> opc, string asm, SDPatternOperator op> {
4006-
def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>,
4026+
multiclass sve2_int_un_pred_arit<bits<2> opc, string asm, SDPatternOperator op> {
4027+
def _B : sve2_int_un_pred_arit<0b00, opc, asm, ZPR8>,
40074028
SVEPseudo2Instr<NAME # _B, 1>;
4008-
def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>,
4029+
def _H : sve2_int_un_pred_arit<0b01, opc, asm, ZPR16>,
40094030
SVEPseudo2Instr<NAME # _H, 1>;
4010-
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>,
4031+
def _S : sve2_int_un_pred_arit<0b10, opc, asm, ZPR32>,
40114032
SVEPseudo2Instr<NAME # _S, 1>;
4012-
def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>,
4033+
def _D : sve2_int_un_pred_arit<0b11, opc, asm, ZPR64>,
40134034
SVEPseudo2Instr<NAME # _D, 1>;
40144035

40154036
def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
@@ -4028,6 +4049,13 @@ multiclass sve2_int_un_pred_arit<bits<3> opc, string asm, SDPatternOperator op>
40284049
defm : SVE_3_Op_Undef_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
40294050
}
40304051

4052+
multiclass sve2_int_un_pred_arit_z<bits<2> opc, string asm> {
4053+
def _B : sve2_int_un_pred_arit_z<0b00, opc, asm, ZPR8>;
4054+
def _H : sve2_int_un_pred_arit_z<0b01, opc, asm, ZPR16>;
4055+
def _S : sve2_int_un_pred_arit_z<0b10, opc, asm, ZPR32>;
4056+
def _D : sve2_int_un_pred_arit_z<0b11, opc, asm, ZPR64>;
4057+
}
4058+
40314059
//===----------------------------------------------------------------------===//
40324060
// SVE2 Widening Integer Arithmetic Group
40334061
//===----------------------------------------------------------------------===//

‎llvm/test/MC/AArch64/SVE2/sqabs-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
sqabs z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: sqabs z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

‎llvm/test/MC/AArch64/SVE2/sqneg-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
sqneg z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: sqneg z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

‎llvm/test/MC/AArch64/SVE2/urecpe-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
urecpe z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: urecpe z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

‎llvm/test/MC/AArch64/SVE2/ursqrte-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
ursqrte z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: ursqrte z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

‎llvm/test/MC/AArch64/SVE2p2/sqabs_z-diagnostics.s

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
2+
3+
// ------------------------------------------------------------------------- //
4+
// Invalid element width
5+
6+
sqabs z31.b, p7/z, z31.h
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
8+
// CHECK-NEXT: sqabs z31.b, p7/z, z31.h
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
sqabs z31.d, p7/z, z31.s
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
13+
// CHECK-NEXT: sqabs z31.d, p7/z, z31.s
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
// ------------------------------------------------------------------------- //
17+
// Invalid predicate
18+
19+
sqabs z31.b, p8/z, z31.b
20+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
21+
// CHECK-NEXT: sqabs z31.b, p8/z, z31.b
22+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23+
24+
// --------------------------------------------------------------------------//
25+
// Negative tests for instructions that are incompatible with movprfx
26+
27+
movprfx z0.h, p0/z, z7.h
28+
sqabs z0.h, p0/z, z3.h
29+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
30+
// CHECK-NEXT: sqabs z0.h, p0/z, z3.h
31+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32+
33+
movprfx z0, z7
34+
sqabs z0.h, p0/z, z3.h
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
36+
// CHECK-NEXT: sqabs z0.h, p0/z, z3.h
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/sqabs_z.s

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
9+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
10+
// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
12+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
13+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
14+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
15+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
16+
17+
sqabs z0.b, p0/z, z0.b // 01000100-00001010-10100000-00000000
18+
// CHECK-INST: sqabs z0.b, p0/z, z0.b
19+
// CHECK-ENCODING: [0x00,0xa0,0x0a,0x44]
20+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
21+
// CHECK-UNKNOWN: 440aa000 <unknown>
22+
23+
sqabs z21.h, p5/z, z10.h // 01000100-01001010-10110101-01010101
24+
// CHECK-INST: sqabs z21.h, p5/z, z10.h
25+
// CHECK-ENCODING: [0x55,0xb5,0x4a,0x44]
26+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
27+
// CHECK-UNKNOWN: 444ab555 <unknown>
28+
29+
sqabs z23.s, p3/z, z13.s // 01000100-10001010-10101101-10110111
30+
// CHECK-INST: sqabs z23.s, p3/z, z13.s
31+
// CHECK-ENCODING: [0xb7,0xad,0x8a,0x44]
32+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
33+
// CHECK-UNKNOWN: 448aadb7 <unknown>
34+
35+
sqabs z31.d, p7/z, z31.d // 01000100-11001010-10111111-11111111
36+
// CHECK-INST: sqabs z31.d, p7/z, z31.d
37+
// CHECK-ENCODING: [0xff,0xbf,0xca,0x44]
38+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
39+
// CHECK-UNKNOWN: 44cabfff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/sqneg_z-diagnostics.s

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
2+
3+
// ------------------------------------------------------------------------- //
4+
// Invalid element width
5+
6+
sqneg z31.b, p7/z, z31.h
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
8+
// CHECK-NEXT: sqneg z31.b, p7/z, z31.h
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
sqneg z31.d, p7/z, z31.s
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
13+
// CHECK-NEXT: sqneg z31.d, p7/z, z31.s
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
// ------------------------------------------------------------------------- //
17+
// Invalid predicate
18+
19+
sqneg z31.b, p8/z, z31.b
20+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
21+
// CHECK-NEXT: sqneg z31.b, p8/z, z31.b
22+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23+
24+
// --------------------------------------------------------------------------//
25+
// Negative tests for instructions that are incompatible with movprfx
26+
27+
movprfx z0.h, p0/z, z7.h
28+
sqneg z0.h, p0/z, z3.h
29+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
30+
// CHECK-NEXT: sqneg z0.h, p0/z, z3.h
31+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32+
33+
movprfx z0, z7
34+
sqneg z0.h, p0/z, z3.h
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
36+
// CHECK-NEXT: sqneg z0.h, p0/z, z3.h
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/sqneg_z.s

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
9+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
10+
// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
12+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
13+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
14+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
15+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
16+
17+
sqneg z0.b, p0/z, z0.b // 01000100-00001011-10100000-00000000
18+
// CHECK-INST: sqneg z0.b, p0/z, z0.b
19+
// CHECK-ENCODING: [0x00,0xa0,0x0b,0x44]
20+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
21+
// CHECK-UNKNOWN: 440ba000 <unknown>
22+
23+
sqneg z23.h, p3/z, z13.h // 01000100-01001011-10101101-10110111
24+
// CHECK-INST: sqneg z23.h, p3/z, z13.h
25+
// CHECK-ENCODING: [0xb7,0xad,0x4b,0x44]
26+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
27+
// CHECK-UNKNOWN: 444badb7 <unknown>
28+
29+
sqneg z21.s, p5/z, z10.s // 01000100-10001011-10110101-01010101
30+
// CHECK-INST: sqneg z21.s, p5/z, z10.s
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// CHECK-ENCODING: [0x55,0xb5,0x8b,0x44]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 448bb555 <unknown>
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sqneg z31.d, p7/z, z31.d // 01000100-11001011-10111111-11111111
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// CHECK-INST: sqneg z31.d, p7/z, z31.d
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// CHECK-ENCODING: [0xff,0xbf,0xcb,0x44]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 44cbbfff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/urecpe_z-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid element width
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urecpe z31.b, p7/z, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: urecpe z31.b, p7/z, z31.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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urecpe z31.h, p7/z, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: urecpe z31.h, p7/z, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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urecpe z31.s, p7/z, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: urecpe z31.s, p7/z, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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urecpe z31.d, p7/z, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: urecpe z31.d, p7/z, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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urecpe z0.s, p8/z, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: urecpe z0.s, p8/z, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.s, p0/z, z7.s
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urecpe z0.s, p0/z, z3.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: urecpe z0.s, p0/z, z3.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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urecpe z0.s, p0/z, z3.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: urecpe z0.s, p0/z, z3.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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