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[AMDGPU] Pattern for v_xor3_b32
This also allows three op patterns to use increased constant bus limit of GFX10. Differential Revision: https://reviews.llvm.org/D61763 llvm-svn: 360395
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‎llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -560,7 +560,9 @@ class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : PatFrag<
560560
if (!Operands[i]->isDivergent() &&
561561
!isInlineImmediate(Operands[i].getNode())) {
562562
ConstantBusUses++;
563-
if (ConstantBusUses >= 2)
563+
// This uses AMDGPU::V_ADD3_U32, but all three operand instructions
564+
// have the same constant bus limit.
565+
if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32))
564566
return false;
565567
}
566568
}
@@ -625,6 +627,7 @@ def : ThreeOp_i32_Pats<xor, add, V_XAD_U32>;
625627

626628
let SubtargetPredicate = isGFX10Plus in {
627629
def V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
630+
def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32>;
628631
} // End SubtargetPredicate = isGFX10Plus
629632

630633
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/AMDGPU/add3.ll

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
33
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4+
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
45

56
; ===================================================================================
67
; V_ADD3_U32
@@ -17,6 +18,11 @@ define amdgpu_ps float @add3(i32 %a, i32 %b, i32 %c) {
1718
; GFX9: ; %bb.0:
1819
; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2
1920
; GFX9-NEXT: ; return to shader part epilog
21+
;
22+
; GFX10-LABEL: add3:
23+
; GFX10: ; %bb.0:
24+
; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2
25+
; GFX10-NEXT: ; return to shader part epilog
2026
%x = add i32 %a, %b
2127
%result = add i32 %x, %c
2228
%bc = bitcast i32 %result to float
@@ -36,6 +42,12 @@ define amdgpu_ps float @mad_no_add3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
3642
; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v4
3743
; GFX9-NEXT: v_mad_u32_u24 v0, v2, v3, v0
3844
; GFX9-NEXT: ; return to shader part epilog
45+
;
46+
; GFX10-LABEL: mad_no_add3:
47+
; GFX10: ; %bb.0:
48+
; GFX10-NEXT: v_mad_u32_u24 v0, v0, v1, v4
49+
; GFX10-NEXT: v_mad_u32_u24 v0, v2, v3, v0
50+
; GFX10-NEXT: ; return to shader part epilog
3951
%a0 = shl i32 %a, 8
4052
%a1 = lshr i32 %a0, 8
4153
%b0 = shl i32 %b, 8
@@ -69,6 +81,11 @@ define amdgpu_ps float @add3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
6981
; GFX9-NEXT: s_add_i32 s3, s3, s2
7082
; GFX9-NEXT: v_add_u32_e32 v0, s3, v0
7183
; GFX9-NEXT: ; return to shader part epilog
84+
;
85+
; GFX10-LABEL: add3_vgpr_b:
86+
; GFX10: ; %bb.0:
87+
; GFX10-NEXT: v_add3_u32 v0, s3, s2, v0
88+
; GFX10-NEXT: ; return to shader part epilog
7289
%x = add i32 %a, %b
7390
%result = add i32 %x, %c
7491
%bc = bitcast i32 %result to float
@@ -86,6 +103,11 @@ define amdgpu_ps float @add3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
86103
; GFX9: ; %bb.0:
87104
; GFX9-NEXT: v_add3_u32 v0, v1, v2, v0
88105
; GFX9-NEXT: ; return to shader part epilog
106+
;
107+
; GFX10-LABEL: add3_vgpr_all2:
108+
; GFX10: ; %bb.0:
109+
; GFX10-NEXT: v_add3_u32 v0, v1, v2, v0
110+
; GFX10-NEXT: ; return to shader part epilog
89111
%x = add i32 %b, %c
90112
%result = add i32 %a, %x
91113
%bc = bitcast i32 %result to float
@@ -103,6 +125,11 @@ define amdgpu_ps float @add3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
103125
; GFX9: ; %bb.0:
104126
; GFX9-NEXT: v_add3_u32 v0, s2, v0, v1
105127
; GFX9-NEXT: ; return to shader part epilog
128+
;
129+
; GFX10-LABEL: add3_vgpr_bc:
130+
; GFX10: ; %bb.0:
131+
; GFX10-NEXT: v_add3_u32 v0, s2, v0, v1
132+
; GFX10-NEXT: ; return to shader part epilog
106133
%x = add i32 %a, %b
107134
%result = add i32 %x, %c
108135
%bc = bitcast i32 %result to float
@@ -120,6 +147,11 @@ define amdgpu_ps float @add3_vgpr_const(i32 %a, i32 %b) {
120147
; GFX9: ; %bb.0:
121148
; GFX9-NEXT: v_add3_u32 v0, v0, v1, 16
122149
; GFX9-NEXT: ; return to shader part epilog
150+
;
151+
; GFX10-LABEL: add3_vgpr_const:
152+
; GFX10: ; %bb.0:
153+
; GFX10-NEXT: v_add3_u32 v0, v0, v1, 16
154+
; GFX10-NEXT: ; return to shader part epilog
123155
%x = add i32 %a, %b
124156
%result = add i32 %x, 16
125157
%bc = bitcast i32 %result to float
@@ -139,6 +171,12 @@ define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x
139171
; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2
140172
; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3
141173
; GFX9-NEXT: ; return to shader part epilog
174+
;
175+
; GFX10-LABEL: add3_multiuse_outer:
176+
; GFX10: ; %bb.0:
177+
; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2
178+
; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3
179+
; GFX10-NEXT: ; return to shader part epilog
142180
%inner = add i32 %a, %b
143181
%outer = add i32 %inner, %c
144182
%x1 = mul i32 %outer, %x
@@ -160,6 +198,12 @@ define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
160198
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
161199
; GFX9-NEXT: v_add_u32_e32 v1, v0, v2
162200
; GFX9-NEXT: ; return to shader part epilog
201+
;
202+
; GFX10-LABEL: add3_multiuse_inner:
203+
; GFX10: ; %bb.0:
204+
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
205+
; GFX10-NEXT: v_add_nc_u32_e32 v1, v0, v2
206+
; GFX10-NEXT: ; return to shader part epilog
163207
%inner = add i32 %a, %b
164208
%outer = add i32 %inner, %c
165209
%r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
@@ -190,6 +234,15 @@ define amdgpu_ps float @add3_uniform_vgpr(float inreg %a, float inreg %b, float
190234
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
191235
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
192236
; GFX9-NEXT: ; return to shader part epilog
237+
;
238+
; GFX10-LABEL: add3_uniform_vgpr:
239+
; GFX10: ; %bb.0:
240+
; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0
241+
; GFX10-NEXT: v_add_f32_e64 v2, s2, 1.0
242+
; GFX10-NEXT: v_add_f32_e64 v0, 0x40400000, s4
243+
; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1
244+
; GFX10-NEXT: v_add_nc_u32_e32 v0, v1, v0
245+
; GFX10-NEXT: ; return to shader part epilog
193246
%a1 = fadd float %a, 1.0
194247
%b2 = fadd float %b, 2.0
195248
%c3 = fadd float %c, 3.0

‎llvm/test/CodeGen/AMDGPU/add_shl.ll

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
33
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4+
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
45

56
; ===================================================================================
67
; V_ADD_LSHL_U32
@@ -17,6 +18,11 @@ define amdgpu_ps float @add_shl(i32 %a, i32 %b, i32 %c) {
1718
; GFX9: ; %bb.0:
1819
; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, v2
1920
; GFX9-NEXT: ; return to shader part epilog
21+
;
22+
; GFX10-LABEL: add_shl:
23+
; GFX10: ; %bb.0:
24+
; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, v2
25+
; GFX10-NEXT: ; return to shader part epilog
2026
%x = add i32 %a, %b
2127
%result = shl i32 %x, %c
2228
%bc = bitcast i32 %result to float
@@ -35,6 +41,11 @@ define amdgpu_ps float @add_shl_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
3541
; GFX9-NEXT: s_add_i32 s2, s2, s3
3642
; GFX9-NEXT: v_lshlrev_b32_e64 v0, v0, s2
3743
; GFX9-NEXT: ; return to shader part epilog
44+
;
45+
; GFX10-LABEL: add_shl_vgpr_c:
46+
; GFX10: ; %bb.0:
47+
; GFX10-NEXT: v_add_lshl_u32 v0, s2, s3, v0
48+
; GFX10-NEXT: ; return to shader part epilog
3849
%x = add i32 %a, %b
3950
%result = shl i32 %x, %c
4051
%bc = bitcast i32 %result to float
@@ -52,6 +63,11 @@ define amdgpu_ps float @add_shl_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
5263
; GFX9: ; %bb.0:
5364
; GFX9-NEXT: v_add_lshl_u32 v0, v0, s2, v1
5465
; GFX9-NEXT: ; return to shader part epilog
66+
;
67+
; GFX10-LABEL: add_shl_vgpr_ac:
68+
; GFX10: ; %bb.0:
69+
; GFX10-NEXT: v_add_lshl_u32 v0, v0, s2, v1
70+
; GFX10-NEXT: ; return to shader part epilog
5571
%x = add i32 %a, %b
5672
%result = shl i32 %x, %c
5773
%bc = bitcast i32 %result to float
@@ -69,6 +85,11 @@ define amdgpu_ps float @add_shl_vgpr_const(i32 %a, i32 %b) {
6985
; GFX9: ; %bb.0:
7086
; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, 9
7187
; GFX9-NEXT: ; return to shader part epilog
88+
;
89+
; GFX10-LABEL: add_shl_vgpr_const:
90+
; GFX10: ; %bb.0:
91+
; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, 9
92+
; GFX10-NEXT: ; return to shader part epilog
7293
%x = add i32 %a, %b
7394
%result = shl i32 %x, 9
7495
%bc = bitcast i32 %result to float
@@ -87,6 +108,11 @@ define amdgpu_ps float @add_shl_vgpr_const_inline_const(i32 %a) {
87108
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7e800
88109
; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1
89110
; GFX9-NEXT: ; return to shader part epilog
111+
;
112+
; GFX10-LABEL: add_shl_vgpr_const_inline_const:
113+
; GFX10: ; %bb.0:
114+
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x7e800
115+
; GFX10-NEXT: ; return to shader part epilog
90116
%x = add i32 %a, 1012
91117
%result = shl i32 %x, 9
92118
%bc = bitcast i32 %result to float
@@ -108,6 +134,11 @@ define amdgpu_ps float @add_shl_vgpr_inline_const_x2(i32 %a) {
108134
; GFX9-NEXT: v_mov_b32_e32 v1, 0x600
109135
; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1
110136
; GFX9-NEXT: ; return to shader part epilog
137+
;
138+
; GFX10-LABEL: add_shl_vgpr_inline_const_x2:
139+
; GFX10: ; %bb.0:
140+
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x600
141+
; GFX10-NEXT: ; return to shader part epilog
111142
%x = add i32 %a, 3
112143
%result = shl i32 %x, 9
113144
%bc = bitcast i32 %result to float

‎llvm/test/CodeGen/AMDGPU/and_or.ll

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
33
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4+
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
45

56
; ===================================================================================
67
; V_AND_OR_B32
@@ -17,6 +18,11 @@ define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {
1718
; GFX9: ; %bb.0:
1819
; GFX9-NEXT: v_and_or_b32 v0, v0, v1, v2
1920
; GFX9-NEXT: ; return to shader part epilog
21+
;
22+
; GFX10-LABEL: and_or:
23+
; GFX10: ; %bb.0:
24+
; GFX10-NEXT: v_and_or_b32 v0, v0, v1, v2
25+
; GFX10-NEXT: ; return to shader part epilog
2026
%x = and i32 %a, %b
2127
%result = or i32 %x, %c
2228
%bc = bitcast i32 %result to float
@@ -36,6 +42,11 @@ define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
3642
; GFX9-NEXT: v_and_b32_e32 v0, s2, v0
3743
; GFX9-NEXT: v_or_b32_e32 v0, s3, v0
3844
; GFX9-NEXT: ; return to shader part epilog
45+
;
46+
; GFX10-LABEL: and_or_vgpr_b:
47+
; GFX10: ; %bb.0:
48+
; GFX10-NEXT: v_and_or_b32 v0, s2, v0, s3
49+
; GFX10-NEXT: ; return to shader part epilog
3950
%x = and i32 %a, %b
4051
%result = or i32 %x, %c
4152
%bc = bitcast i32 %result to float
@@ -53,6 +64,11 @@ define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
5364
; GFX9: ; %bb.0:
5465
; GFX9-NEXT: v_and_or_b32 v0, v0, v1, s2
5566
; GFX9-NEXT: ; return to shader part epilog
67+
;
68+
; GFX10-LABEL: and_or_vgpr_ab:
69+
; GFX10: ; %bb.0:
70+
; GFX10-NEXT: v_and_or_b32 v0, v0, v1, s2
71+
; GFX10-NEXT: ; return to shader part epilog
5672
%x = and i32 %a, %b
5773
%result = or i32 %x, %c
5874
%bc = bitcast i32 %result to float
@@ -70,6 +86,11 @@ define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {
7086
; GFX9: ; %bb.0:
7187
; GFX9-NEXT: v_and_or_b32 v0, v0, 4, v1
7288
; GFX9-NEXT: ; return to shader part epilog
89+
;
90+
; GFX10-LABEL: and_or_vgpr_const:
91+
; GFX10: ; %bb.0:
92+
; GFX10-NEXT: v_and_or_b32 v0, v0, 4, v1
93+
; GFX10-NEXT: ; return to shader part epilog
7394
%x = and i32 4, %a
7495
%result = or i32 %x, %b
7596
%bc = bitcast i32 %result to float
@@ -88,6 +109,11 @@ define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {
88109
; GFX9-NEXT: v_mov_b32_e32 v1, 0x808
89110
; GFX9-NEXT: v_and_or_b32 v0, v0, 20, v1
90111
; GFX9-NEXT: ; return to shader part epilog
112+
;
113+
; GFX10-LABEL: and_or_vgpr_const_inline_const:
114+
; GFX10: ; %bb.0:
115+
; GFX10-NEXT: v_and_or_b32 v0, v0, 20, 0x808
116+
; GFX10-NEXT: ; return to shader part epilog
91117
%x = and i32 20, %a
92118
%result = or i32 %x, 2056
93119
%bc = bitcast i32 %result to float
@@ -105,6 +131,11 @@ define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
105131
; GFX9: ; %bb.0:
106132
; GFX9-NEXT: v_and_or_b32 v0, v0, 4, 1
107133
; GFX9-NEXT: ; return to shader part epilog
134+
;
135+
; GFX10-LABEL: and_or_vgpr_inline_const_x2:
136+
; GFX10: ; %bb.0:
137+
; GFX10-NEXT: v_and_or_b32 v0, v0, 4, 1
138+
; GFX10-NEXT: ; return to shader part epilog
108139
%x = and i32 4, %a
109140
%result = or i32 %x, 1
110141
%bc = bitcast i32 %result to float

‎llvm/test/CodeGen/AMDGPU/or3.ll

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
33
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4+
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
45

56
; ===================================================================================
67
; V_OR3_B32
@@ -17,6 +18,11 @@ define amdgpu_ps float @or3(i32 %a, i32 %b, i32 %c) {
1718
; GFX9: ; %bb.0:
1819
; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2
1920
; GFX9-NEXT: ; return to shader part epilog
21+
;
22+
; GFX10-LABEL: or3:
23+
; GFX10: ; %bb.0:
24+
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
25+
; GFX10-NEXT: ; return to shader part epilog
2026
%x = or i32 %a, %b
2127
%result = or i32 %x, %c
2228
%bc = bitcast i32 %result to float
@@ -37,6 +43,11 @@ define amdgpu_ps float @or3_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
3743
; GFX9-NEXT: v_or_b32_e32 v0, s2, v0
3844
; GFX9-NEXT: v_or_b32_e32 v0, s3, v0
3945
; GFX9-NEXT: ; return to shader part epilog
46+
;
47+
; GFX10-LABEL: or3_vgpr_a:
48+
; GFX10: ; %bb.0:
49+
; GFX10-NEXT: v_or3_b32 v0, v0, s2, s3
50+
; GFX10-NEXT: ; return to shader part epilog
4051
%x = or i32 %a, %b
4152
%result = or i32 %x, %c
4253
%bc = bitcast i32 %result to float
@@ -54,6 +65,11 @@ define amdgpu_ps float @or3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
5465
; GFX9: ; %bb.0:
5566
; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0
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; GFX9-NEXT: ; return to shader part epilog
68+
;
69+
; GFX10-LABEL: or3_vgpr_all2:
70+
; GFX10: ; %bb.0:
71+
; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
72+
; GFX10-NEXT: ; return to shader part epilog
5773
%x = or i32 %b, %c
5874
%result = or i32 %a, %x
5975
%bc = bitcast i32 %result to float
@@ -71,6 +87,11 @@ define amdgpu_ps float @or3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
7187
; GFX9: ; %bb.0:
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; GFX9-NEXT: v_or3_b32 v0, s2, v0, v1
7389
; GFX9-NEXT: ; return to shader part epilog
90+
;
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; GFX10-LABEL: or3_vgpr_bc:
92+
; GFX10: ; %bb.0:
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; GFX10-NEXT: v_or3_b32 v0, s2, v0, v1
94+
; GFX10-NEXT: ; return to shader part epilog
7495
%x = or i32 %a, %b
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%result = or i32 %x, %c
7697
%bc = bitcast i32 %result to float
@@ -88,6 +109,11 @@ define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) {
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_or3_b32 v0, v1, v0, 64
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; GFX9-NEXT: ; return to shader part epilog
112+
;
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; GFX10-LABEL: or3_vgpr_const:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_or3_b32 v0, v1, v0, 64
116+
; GFX10-NEXT: ; return to shader part epilog
91117
%x = or i32 64, %b
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%result = or i32 %x, %a
93119
%bc = bitcast i32 %result to float

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