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AMDGPU/GlobalISel: Widen s1 SGPR constants during regbankselect
To unambiguously interpret these as 32-bit SGPRs, we need to widen these to s32. This was selecting to a copy from a 64-bit SGPR to a 32-bit SGPR for wave64.
1 parent 2ad4c3c commit 6454391

13 files changed

+1122
-928
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2117,6 +2117,35 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
21172117
unsigned Opc = MI.getOpcode();
21182118
MachineRegisterInfo &MRI = OpdMapper.getMRI();
21192119
switch (Opc) {
2120+
case AMDGPU::G_CONSTANT: {
2121+
Register DstReg = MI.getOperand(0).getReg();
2122+
LLT DstTy = MRI.getType(DstReg);
2123+
if (DstTy != LLT::scalar(1))
2124+
break;
2125+
2126+
const RegisterBank *DstBank =
2127+
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2128+
if (DstBank == &AMDGPU::VCCRegBank)
2129+
break;
2130+
SmallVector<Register, 1> DefRegs(OpdMapper.getVRegs(0));
2131+
if (DefRegs.empty())
2132+
DefRegs.push_back(DstReg);
2133+
2134+
MachineIRBuilder B(MI);
2135+
B.setInsertPt(*MI.getParent(), ++MI.getIterator());
2136+
2137+
Register NewDstReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
2138+
LLVMContext &Ctx = B.getMF().getFunction().getContext();
2139+
2140+
MI.getOperand(0).setReg(NewDstReg);
2141+
uint64_t ConstVal = MI.getOperand(1).getCImm()->getZExtValue();
2142+
MI.getOperand(1).setCImm(
2143+
ConstantInt::get(IntegerType::getInt32Ty(Ctx), ConstVal));
2144+
2145+
MRI.setRegBank(NewDstReg, *DstBank);
2146+
B.buildTrunc(DefRegs[0], NewDstReg);
2147+
return;
2148+
}
21202149
case AMDGPU::G_PHI: {
21212150
Register DstReg = MI.getOperand(0).getReg();
21222151
LLT DstTy = MRI.getType(DstReg);

‎llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ define amdgpu_kernel void @sgpr_trunc_brcond(i32 %cond) {
6868
; WAVE64: ; %bb.0: ; %entry
6969
; WAVE64-NEXT: s_load_dword s0, s[0:1], 0x24
7070
; WAVE64-NEXT: s_waitcnt lgkmcnt(0)
71-
; WAVE64-NEXT: s_xor_b32 s0, s0, -1
71+
; WAVE64-NEXT: s_xor_b32 s0, s0, 1
7272
; WAVE64-NEXT: s_and_b32 s0, s0, 1
7373
; WAVE64-NEXT: s_cmp_lg_u32 s0, 0
7474
; WAVE64-NEXT: s_cbranch_scc1 .LBB3_2
@@ -85,7 +85,7 @@ define amdgpu_kernel void @sgpr_trunc_brcond(i32 %cond) {
8585
; WAVE32: ; %bb.0: ; %entry
8686
; WAVE32-NEXT: s_load_dword s0, s[0:1], 0x24
8787
; WAVE32-NEXT: s_waitcnt lgkmcnt(0)
88-
; WAVE32-NEXT: s_xor_b32 s0, s0, -1
88+
; WAVE32-NEXT: s_xor_b32 s0, s0, 1
8989
; WAVE32-NEXT: s_and_b32 s0, s0, 1
9090
; WAVE32-NEXT: s_cmp_lg_u32 s0, 0
9191
; WAVE32-NEXT: s_cbranch_scc1 .LBB3_2
@@ -116,7 +116,7 @@ define amdgpu_kernel void @brcond_sgpr_trunc_and(i32 %cond0, i32 %cond1) {
116116
; WAVE64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
117117
; WAVE64-NEXT: s_waitcnt lgkmcnt(0)
118118
; WAVE64-NEXT: s_and_b32 s0, s0, s1
119-
; WAVE64-NEXT: s_xor_b32 s0, s0, -1
119+
; WAVE64-NEXT: s_xor_b32 s0, s0, 1
120120
; WAVE64-NEXT: s_and_b32 s0, s0, 1
121121
; WAVE64-NEXT: s_cmp_lg_u32 s0, 0
122122
; WAVE64-NEXT: s_cbranch_scc1 .LBB4_2
@@ -134,7 +134,7 @@ define amdgpu_kernel void @brcond_sgpr_trunc_and(i32 %cond0, i32 %cond1) {
134134
; WAVE32-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
135135
; WAVE32-NEXT: s_waitcnt lgkmcnt(0)
136136
; WAVE32-NEXT: s_and_b32 s0, s0, s1
137-
; WAVE32-NEXT: s_xor_b32 s0, s0, -1
137+
; WAVE32-NEXT: s_xor_b32 s0, s0, 1
138138
; WAVE32-NEXT: s_and_b32 s0, s0, 1
139139
; WAVE32-NEXT: s_cmp_lg_u32 s0, 0
140140
; WAVE32-NEXT: s_cbranch_scc1 .LBB4_2

‎llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll

Lines changed: 142 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,142 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -global-isel -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=WAVE64 %s
3+
; RUN: llc -global-isel -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck -check-prefix=WAVE32 %s
4+
5+
; This was mishandling the constant true and false values used as a
6+
; scalar branch condition.
7+
8+
define void @br_false() {
9+
; WAVE64-LABEL: br_false:
10+
; WAVE64: ; %bb.0: ; %.exit
11+
; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
12+
; WAVE64-NEXT: .LBB0_1: ; %bb0
13+
; WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1
14+
; WAVE64-NEXT: s_mov_b32 s4, 1
15+
; WAVE64-NEXT: s_cmp_lg_u32 s4, 0
16+
; WAVE64-NEXT: s_cbranch_scc1 .LBB0_1
17+
; WAVE64-NEXT: ; %bb.2: ; %.exit5
18+
; WAVE64-NEXT: s_setpc_b64 s[30:31]
19+
;
20+
; WAVE32-LABEL: br_false:
21+
; WAVE32: ; %bb.0: ; %.exit
22+
; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
23+
; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
24+
; WAVE32-NEXT: .LBB0_1: ; %bb0
25+
; WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1
26+
; WAVE32-NEXT: s_mov_b32 s4, 1
27+
; WAVE32-NEXT: s_cmp_lg_u32 s4, 0
28+
; WAVE32-NEXT: s_cbranch_scc1 .LBB0_1
29+
; WAVE32-NEXT: ; %bb.2: ; %.exit5
30+
; WAVE32-NEXT: s_setpc_b64 s[30:31]
31+
.exit:
32+
br label %bb0
33+
34+
bb0:
35+
br i1 false, label %.exit5, label %bb0
36+
37+
.exit5:
38+
ret void
39+
}
40+
41+
define void @br_true() {
42+
; WAVE64-LABEL: br_true:
43+
; WAVE64: ; %bb.0: ; %.exit
44+
; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
45+
; WAVE64-NEXT: .LBB1_1: ; %bb0
46+
; WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1
47+
; WAVE64-NEXT: s_mov_b32 s4, 0
48+
; WAVE64-NEXT: s_cmp_lg_u32 s4, 0
49+
; WAVE64-NEXT: s_cbranch_scc1 .LBB1_1
50+
; WAVE64-NEXT: ; %bb.2: ; %.exit5
51+
; WAVE64-NEXT: s_setpc_b64 s[30:31]
52+
;
53+
; WAVE32-LABEL: br_true:
54+
; WAVE32: ; %bb.0: ; %.exit
55+
; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
56+
; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
57+
; WAVE32-NEXT: .LBB1_1: ; %bb0
58+
; WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1
59+
; WAVE32-NEXT: s_mov_b32 s4, 0
60+
; WAVE32-NEXT: s_cmp_lg_u32 s4, 0
61+
; WAVE32-NEXT: s_cbranch_scc1 .LBB1_1
62+
; WAVE32-NEXT: ; %bb.2: ; %.exit5
63+
; WAVE32-NEXT: s_setpc_b64 s[30:31]
64+
.exit:
65+
br label %bb0
66+
67+
bb0:
68+
br i1 true, label %.exit5, label %bb0
69+
70+
.exit5:
71+
ret void
72+
}
73+
74+
define void @br_undef() {
75+
; WAVE64-LABEL: br_undef:
76+
; WAVE64: ; %bb.0: ; %.exit
77+
; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
78+
; WAVE64-NEXT: .LBB2_1: ; %bb0
79+
; WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1
80+
; WAVE64-NEXT: ; implicit-def: $sgpr4
81+
; WAVE64-NEXT: s_and_b32 s4, s4, 1
82+
; WAVE64-NEXT: s_cmp_lg_u32 s4, 0
83+
; WAVE64-NEXT: s_cbranch_scc1 .LBB2_1
84+
; WAVE64-NEXT: ; %bb.2: ; %.exit5
85+
; WAVE64-NEXT: s_setpc_b64 s[30:31]
86+
;
87+
; WAVE32-LABEL: br_undef:
88+
; WAVE32: ; %bb.0: ; %.exit
89+
; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
90+
; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
91+
; WAVE32-NEXT: .LBB2_1: ; %bb0
92+
; WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1
93+
; WAVE32-NEXT: ; implicit-def: $sgpr4
94+
; WAVE32-NEXT: s_and_b32 s4, s4, 1
95+
; WAVE32-NEXT: s_cmp_lg_u32 s4, 0
96+
; WAVE32-NEXT: s_cbranch_scc1 .LBB2_1
97+
; WAVE32-NEXT: ; %bb.2: ; %.exit5
98+
; WAVE32-NEXT: s_setpc_b64 s[30:31]
99+
.exit:
100+
br label %bb0
101+
102+
bb0:
103+
br i1 undef, label %.exit5, label %bb0
104+
105+
.exit5:
106+
ret void
107+
}
108+
109+
define void @br_poison() {
110+
; WAVE64-LABEL: br_poison:
111+
; WAVE64: ; %bb.0: ; %.exit
112+
; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
113+
; WAVE64-NEXT: .LBB3_1: ; %bb0
114+
; WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1
115+
; WAVE64-NEXT: ; implicit-def: $sgpr4
116+
; WAVE64-NEXT: s_and_b32 s4, s4, 1
117+
; WAVE64-NEXT: s_cmp_lg_u32 s4, 0
118+
; WAVE64-NEXT: s_cbranch_scc1 .LBB3_1
119+
; WAVE64-NEXT: ; %bb.2: ; %.exit5
120+
; WAVE64-NEXT: s_setpc_b64 s[30:31]
121+
;
122+
; WAVE32-LABEL: br_poison:
123+
; WAVE32: ; %bb.0: ; %.exit
124+
; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
125+
; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
126+
; WAVE32-NEXT: .LBB3_1: ; %bb0
127+
; WAVE32-NEXT: ; =>This Inner Loop Header: Depth=1
128+
; WAVE32-NEXT: ; implicit-def: $sgpr4
129+
; WAVE32-NEXT: s_and_b32 s4, s4, 1
130+
; WAVE32-NEXT: s_cmp_lg_u32 s4, 0
131+
; WAVE32-NEXT: s_cbranch_scc1 .LBB3_1
132+
; WAVE32-NEXT: ; %bb.2: ; %.exit5
133+
; WAVE32-NEXT: s_setpc_b64 s[30:31]
134+
.exit:
135+
br label %bb0
136+
137+
bb0:
138+
br i1 poison, label %.exit5, label %bb0
139+
140+
.exit5:
141+
ret void
142+
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -584,3 +584,53 @@ body: |
584584
%7:vgpr(p999) = G_CONSTANT i64 18446744004990098135
585585
S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7
586586
...
587+
588+
---
589+
name: zext_sgpr_s1_to_sgpr_s32
590+
legalized: true
591+
regBankSelected: true
592+
tracksRegLiveness: true
593+
594+
body: |
595+
; WAVE64-LABEL: name: zext_sgpr_s1_to_sgpr_s32
596+
; WAVE64: bb.0:
597+
; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
598+
; WAVE64-NEXT: {{ $}}
599+
; WAVE64-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -1
600+
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B64_]]
601+
; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
602+
; WAVE64-NEXT: $scc = COPY [[S_AND_B32_]]
603+
; WAVE64-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
604+
; WAVE64-NEXT: S_BRANCH %bb.2
605+
; WAVE64-NEXT: {{ $}}
606+
; WAVE64-NEXT: bb.1:
607+
; WAVE64-NEXT: successors: %bb.2(0x80000000)
608+
; WAVE64-NEXT: {{ $}}
609+
; WAVE64-NEXT: {{ $}}
610+
; WAVE64-NEXT: bb.2:
611+
; WAVE32-LABEL: name: zext_sgpr_s1_to_sgpr_s32
612+
; WAVE32: bb.0:
613+
; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
614+
; WAVE32-NEXT: {{ $}}
615+
; WAVE32-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
616+
; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], 1, implicit-def $scc
617+
; WAVE32-NEXT: $scc = COPY [[S_AND_B32_]]
618+
; WAVE32-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
619+
; WAVE32-NEXT: S_BRANCH %bb.2
620+
; WAVE32-NEXT: {{ $}}
621+
; WAVE32-NEXT: bb.1:
622+
; WAVE32-NEXT: successors: %bb.2(0x80000000)
623+
; WAVE32-NEXT: {{ $}}
624+
; WAVE32-NEXT: {{ $}}
625+
; WAVE32-NEXT: bb.2:
626+
bb.0:
627+
%0:sgpr(s1) = G_CONSTANT i1 true
628+
%1:sgpr(s32) = G_ZEXT %0
629+
G_BRCOND %1, %bb.1
630+
G_BR %bb.2
631+
632+
bb.1:
633+
634+
bb.2:
635+
636+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@ define amdgpu_kernel void @set_inactive_scc(ptr addrspace(1) %out, i32 %in, <4 x
4848
; GCN-NEXT: s_buffer_load_dword s2, s[4:7], 0x0
4949
; GCN-NEXT: s_load_dword s3, s[0:1], 0x2c
5050
; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
51+
; GCN-NEXT: s_mov_b32 s4, 1
5152
; GCN-NEXT: s_waitcnt lgkmcnt(0)
5253
; GCN-NEXT: s_cmp_lg_u32 s2, 56
5354
; GCN-NEXT: s_cselect_b32 s2, 1, 0
@@ -63,19 +64,16 @@ define amdgpu_kernel void @set_inactive_scc(ptr addrspace(1) %out, i32 %in, <4 x
6364
; GCN-NEXT: s_mov_b32 s3, 0xf000
6465
; GCN-NEXT: s_mov_b32 s4, 0
6566
; GCN-NEXT: buffer_store_dword v1, off, s[0:3], 0
66-
; GCN-NEXT: s_branch .LBB2_3
67-
; GCN-NEXT: .LBB2_2:
68-
; GCN-NEXT: s_mov_b32 s4, -1
69-
; GCN-NEXT: .LBB2_3: ; %Flow
70-
; GCN-NEXT: s_xor_b32 s2, s4, -1
67+
; GCN-NEXT: .LBB2_2: ; %Flow
68+
; GCN-NEXT: s_xor_b32 s2, s4, 1
7169
; GCN-NEXT: s_and_b32 s2, s2, 1
7270
; GCN-NEXT: s_cmp_lg_u32 s2, 0
73-
; GCN-NEXT: s_cbranch_scc1 .LBB2_5
74-
; GCN-NEXT: ; %bb.4: ; %.zero
71+
; GCN-NEXT: s_cbranch_scc1 .LBB2_4
72+
; GCN-NEXT: ; %bb.3: ; %.zero
7573
; GCN-NEXT: s_mov_b32 s2, -1
7674
; GCN-NEXT: s_mov_b32 s3, 0xf000
7775
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
78-
; GCN-NEXT: .LBB2_5: ; %.exit
76+
; GCN-NEXT: .LBB2_4: ; %.exit
7977
; GCN-NEXT: s_endpgm
8078
%val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 0, i32 0)
8179
%cmp = icmp eq i32 %val, 56

‎llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@ define amdgpu_kernel void @localize_constants(i1 %cond) {
88
; GFX9-LABEL: localize_constants:
99
; GFX9: ; %bb.0: ; %entry
1010
; GFX9-NEXT: s_load_dword s1, s[4:5], 0x0
11-
; GFX9-NEXT: s_mov_b32 s0, -1
11+
; GFX9-NEXT: s_mov_b32 s0, 1
1212
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
13-
; GFX9-NEXT: s_xor_b32 s1, s1, -1
13+
; GFX9-NEXT: s_xor_b32 s1, s1, 1
1414
; GFX9-NEXT: s_and_b32 s1, s1, 1
1515
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
1616
; GFX9-NEXT: s_cbranch_scc0 .LBB0_2
@@ -35,7 +35,7 @@ define amdgpu_kernel void @localize_constants(i1 %cond) {
3535
; GFX9-NEXT: global_store_dword v[0:1], v0, off
3636
; GFX9-NEXT: s_waitcnt vmcnt(0)
3737
; GFX9-NEXT: .LBB0_2: ; %Flow
38-
; GFX9-NEXT: s_xor_b32 s0, s0, -1
38+
; GFX9-NEXT: s_xor_b32 s0, s0, 1
3939
; GFX9-NEXT: s_and_b32 s0, s0, 1
4040
; GFX9-NEXT: s_cmp_lg_u32 s0, 0
4141
; GFX9-NEXT: s_cbranch_scc1 .LBB0_4
@@ -96,9 +96,9 @@ define amdgpu_kernel void @localize_globals(i1 %cond) {
9696
; GFX9-LABEL: localize_globals:
9797
; GFX9: ; %bb.0: ; %entry
9898
; GFX9-NEXT: s_load_dword s1, s[4:5], 0x0
99-
; GFX9-NEXT: s_mov_b32 s0, -1
99+
; GFX9-NEXT: s_mov_b32 s0, 1
100100
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
101-
; GFX9-NEXT: s_xor_b32 s1, s1, -1
101+
; GFX9-NEXT: s_xor_b32 s1, s1, 1
102102
; GFX9-NEXT: s_and_b32 s1, s1, 1
103103
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
104104
; GFX9-NEXT: s_cbranch_scc0 .LBB1_2
@@ -120,7 +120,7 @@ define amdgpu_kernel void @localize_globals(i1 %cond) {
120120
; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
121121
; GFX9-NEXT: s_waitcnt vmcnt(0)
122122
; GFX9-NEXT: .LBB1_2: ; %Flow
123-
; GFX9-NEXT: s_xor_b32 s0, s0, -1
123+
; GFX9-NEXT: s_xor_b32 s0, s0, 1
124124
; GFX9-NEXT: s_and_b32 s0, s0, 1
125125
; GFX9-NEXT: s_cmp_lg_u32 s0, 0
126126
; GFX9-NEXT: s_cbranch_scc1 .LBB1_4

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -51,8 +51,9 @@ legalized: true
5151
body: |
5252
bb.0:
5353
; CHECK-LABEL: name: kill_constant_true
54-
; CHECK: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
55-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
54+
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
55+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[C]](s32)
56+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
5657
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), [[COPY]](s1)
5758
%0:_(s1) = G_CONSTANT i1 true
5859
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), %0
@@ -65,8 +66,9 @@ legalized: true
6566
body: |
6667
bb.0:
6768
; CHECK-LABEL: name: kill_constant_false
68-
; CHECK: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
69-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
69+
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
70+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[C]](s32)
71+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
7072
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), [[COPY]](s1)
7173
%0:_(s1) = G_CONSTANT i1 false
7274
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), %0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -51,8 +51,9 @@ legalized: true
5151
body: |
5252
bb.0:
5353
; CHECK-LABEL: name: wqm_demote_constant_true
54-
; CHECK: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
55-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
54+
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
55+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[C]](s32)
56+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
5657
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.wqm.demote), [[COPY]](s1)
5758
%0:_(s1) = G_CONSTANT i1 true
5859
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.wqm.demote), %0
@@ -65,8 +66,9 @@ legalized: true
6566
body: |
6667
bb.0:
6768
; CHECK-LABEL: name: wqm_demote_constant_false
68-
; CHECK: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
69-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
69+
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
70+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[C]](s32)
71+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
7072
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.wqm.demote), [[COPY]](s1)
7173
%0:_(s1) = G_CONSTANT i1 false
7274
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.wqm.demote), %0

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