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author
Kai Luo
committed
Get it working.
1 parent 9931e7e commit 64571c9

27 files changed

+568
-403
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 125 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -242,13 +242,19 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
242242
setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
243243
}
244244

245-
// PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
245+
// PowerPC uses addo,addo_carry,subo,subo_carry to propagate carry.
246246
const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
247247
for (MVT VT : ScalarIntVTs) {
248-
setOperationAction(ISD::ADDC, VT, Legal);
249-
setOperationAction(ISD::ADDE, VT, Legal);
250-
setOperationAction(ISD::SUBC, VT, Legal);
251-
setOperationAction(ISD::SUBE, VT, Legal);
248+
if (VT == MVT::i64 && !isPPC64)
249+
continue;
250+
setOperationAction(ISD::UADDO, VT, Custom);
251+
setOperationAction(ISD::USUBO, VT, Custom);
252+
setOperationAction(ISD::UADDO_CARRY, VT, Custom);
253+
setOperationAction(ISD::USUBO_CARRY, VT, Custom);
254+
setOperationAction(ISD::SADDO, VT, Custom);
255+
setOperationAction(ISD::SSUBO, VT, Custom);
256+
setOperationAction(ISD::SADDO_CARRY, VT, Custom);
257+
setOperationAction(ISD::SSUBO_CARRY, VT, Custom);
252258
}
253259

254260
if (Subtarget.useCRBits()) {
@@ -1841,6 +1847,10 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
18411847
case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
18421848
case PPCISD::STORE_COND:
18431849
return "PPCISD::STORE_COND";
1850+
case PPCISD::ADDC: return "PPCISD::ADDC";
1851+
case PPCISD::ADDE: return "PPCISD::ADDE";
1852+
case PPCISD::SUBC: return "PPCISD::SUBC";
1853+
case PPCISD::SUBE: return "PPCISD::SUBE";
18441854
}
18451855
return nullptr;
18461856
}
@@ -11722,6 +11732,63 @@ SDValue PPCTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
1172211732
llvm_unreachable("ERROR:Should return for all cases within swtich.");
1172311733
}
1172411734

11735+
static SDValue ConvertCarryValueToCarryFlag(SDValue Value, SelectionDAG &DAG) {
11736+
SDLoc DL(Value);
11737+
Value = DAG.getZExtOrTrunc(Value, DL, MVT::i32);
11738+
SDValue Sum = DAG.getNode(PPCISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::i32),
11739+
Value, DAG.getAllOnesConstant(DL, MVT::i32));
11740+
return Sum.getValue(1);
11741+
}
11742+
11743+
static SDValue ConvertCarryFlagToCarryValue(SDValue Flag, EVT CarryType,
11744+
SelectionDAG &DAG) {
11745+
SDLoc DL(Flag);
11746+
SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
11747+
SDValue Carry = DAG.getNode(
11748+
PPCISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero, Flag);
11749+
return DAG.getZExtOrTrunc(Carry, DL, CarryType);
11750+
}
11751+
11752+
SDValue PPCTargetLowering::LowerADDSUBO(SDValue Op, SelectionDAG &DAG) const {
11753+
SDLoc DL(Op);
11754+
SDNode *N = Op.getNode();
11755+
EVT VT = N->getValueType(0);
11756+
EVT CarryType = N->getValueType(1);
11757+
unsigned Opc = N->getOpcode();
11758+
bool IsAdd = (Opc == ISD::UADDO || Opc == ISD::SADDO);
11759+
Opc = IsAdd ? PPCISD::ADDC : PPCISD::SUBC;
11760+
SDValue Sum = DAG.getNode(Opc, DL, DAG.getVTList(VT, MVT::i32),
11761+
N->getOperand(0), N->getOperand(1));
11762+
SDValue Carry = ConvertCarryFlagToCarryValue(Sum.getValue(1), CarryType, DAG);
11763+
if (!IsAdd)
11764+
Carry = DAG.getNode(ISD::XOR, DL, CarryType, Carry,
11765+
DAG.getAllOnesConstant(DL, CarryType));
11766+
return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, Carry);
11767+
}
11768+
11769+
SDValue PPCTargetLowering::LowerADDSUBO_CARRY(SDValue Op,
11770+
SelectionDAG &DAG) const {
11771+
SDLoc DL(Op);
11772+
SDNode *N = Op.getNode();
11773+
unsigned Opc = N->getOpcode();
11774+
EVT VT = N->getValueType(0);
11775+
EVT CarryType = N->getValueType(1);
11776+
SDValue CarryOp = N->getOperand(2);
11777+
bool IsAdd = (Opc == ISD::UADDO_CARRY || Opc == ISD::SADDO_CARRY);
11778+
Opc = IsAdd ? PPCISD::ADDE : PPCISD::SUBE;
11779+
if (!IsAdd)
11780+
CarryOp = DAG.getNode(ISD::XOR, DL, CarryOp.getValueType(), CarryOp,
11781+
DAG.getAllOnesConstant(DL, CarryOp.getValueType()));
11782+
CarryOp = ConvertCarryValueToCarryFlag(CarryOp, DAG);
11783+
SDValue Sum = DAG.getNode(Opc, DL, DAG.getVTList(VT, MVT::i32),
11784+
Op.getOperand(0), Op.getOperand(1), CarryOp);
11785+
CarryOp = ConvertCarryFlagToCarryValue(Sum.getValue(1), CarryType, DAG);
11786+
if (!IsAdd)
11787+
CarryOp = DAG.getNode(ISD::XOR, DL, CarryOp.getValueType(), CarryOp,
11788+
DAG.getAllOnesConstant(DL, CarryOp.getValueType()));
11789+
return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, CarryOp);
11790+
}
11791+
1172511792
/// LowerOperation - Provide custom lowering hooks for some operations.
1172611793
///
1172711794
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
@@ -11815,6 +11882,16 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1181511882
return LowerATOMIC_LOAD_STORE(Op, DAG);
1181611883
case ISD::IS_FPCLASS:
1181711884
return LowerIS_FPCLASS(Op, DAG);
11885+
case ISD::UADDO:
11886+
case ISD::USUBO:
11887+
case ISD::SADDO:
11888+
case ISD::SSUBO:
11889+
return LowerADDSUBO(Op, DAG);
11890+
case ISD::UADDO_CARRY:
11891+
case ISD::USUBO_CARRY:
11892+
case ISD::SADDO_CARRY:
11893+
case ISD::SSUBO_CARRY:
11894+
return LowerADDSUBO_CARRY(Op, DAG);
1181811895
}
1181911896
}
1182011897

@@ -15708,6 +15785,21 @@ static bool isStoreConditional(SDValue Intrin, unsigned &StoreWidth) {
1570815785
return true;
1570915786
}
1571015787

15788+
static SDValue DAGCombineAddc(SDNode *N,
15789+
llvm::PPCTargetLowering::DAGCombinerInfo &DCI) {
15790+
if (N->getOpcode() == PPCISD::ADDC && N->hasAnyUseOfValue(1)) {
15791+
// (ADDC (ADDE 0, 0, C), -1) -> C
15792+
SDValue LHS = N->getOperand(0);
15793+
SDValue RHS = N->getOperand(1);
15794+
if (LHS->getOpcode() == PPCISD::ADDE &&
15795+
isNullConstant(LHS->getOperand(0)) &&
15796+
isNullConstant(LHS->getOperand(1)) && isAllOnesConstant(RHS)) {
15797+
return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2));
15798+
}
15799+
}
15800+
return SDValue();
15801+
}
15802+
1571115803
SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
1571215804
DAGCombinerInfo &DCI) const {
1571315805
SelectionDAG &DAG = DCI.DAG;
@@ -16497,6 +16589,8 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
1649716589
}
1649816590
case ISD::BUILD_VECTOR:
1649916591
return DAGCombineBuildVector(N, DCI);
16592+
case PPCISD::ADDC:
16593+
return DAGCombineAddc(N, DCI);
1650016594
}
1650116595

1650216596
return SDValue();
@@ -16550,6 +16644,16 @@ void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1655016644
Known.Zero = 0xFFFF0000;
1655116645
break;
1655216646
}
16647+
case PPCISD::ADDE: {
16648+
if (Op.getResNo() == 0) {
16649+
// (0|1), _ = ADDE 0, 0, CARRY
16650+
SDValue LHS = Op.getOperand(0);
16651+
SDValue RHS = Op.getOperand(1);
16652+
if (isNullConstant(LHS) && isNullConstant(RHS))
16653+
Known.Zero = ~1U;
16654+
}
16655+
break;
16656+
}
1655316657
case ISD::INTRINSIC_WO_CHAIN: {
1655416658
switch (Op.getConstantOperandVal(0)) {
1655516659
default: break;
@@ -17811,7 +17915,8 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
1781117915
return SDValue();
1781217916

1781317917
SDLoc DL(N);
17814-
SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Glue);
17918+
EVT CarryType = Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
17919+
SDVTList VTs = DAG.getVTList(MVT::i64, CarryType);
1781517920
SDValue Cmp = RHS.getOperand(0);
1781617921
SDValue Z = Cmp.getOperand(0);
1781717922
auto *Constant = cast<ConstantSDNode>(Cmp.getOperand(1));
@@ -17829,11 +17934,13 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
1782917934
SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z,
1783017935
DAG.getConstant(NegConstant, DL, MVT::i64));
1783117936
SDValue AddOrZ = NegConstant != 0 ? Add : Z;
17832-
SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
17833-
AddOrZ, DAG.getConstant(-1ULL, DL, MVT::i64));
17834-
return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),
17937+
SDValue Addc =
17938+
DAG.getNode(ISD::UADDO, DL, DAG.getVTList(MVT::i64, CarryType), AddOrZ,
17939+
DAG.getConstant(-1ULL, DL, MVT::i64));
17940+
return DAG.getNode(ISD::UADDO_CARRY, DL, VTs, LHS,
17941+
DAG.getConstant(0, DL, MVT::i64),
1783517942
SDValue(Addc.getNode(), 1));
17836-
}
17943+
}
1783717944
case ISD::SETEQ: {
1783817945
// when C == 0
1783917946
// --> addze X, (subfic Z, 0).carry
@@ -17844,11 +17951,14 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
1784417951
SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z,
1784517952
DAG.getConstant(NegConstant, DL, MVT::i64));
1784617953
SDValue AddOrZ = NegConstant != 0 ? Add : Z;
17847-
SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
17848-
DAG.getConstant(0, DL, MVT::i64), AddOrZ);
17849-
return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),
17850-
SDValue(Subc.getNode(), 1));
17851-
}
17954+
SDValue Subc =
17955+
DAG.getNode(ISD::USUBO, DL, DAG.getVTList(MVT::i64, CarryType),
17956+
DAG.getConstant(0, DL, MVT::i64), AddOrZ);
17957+
SDValue Invert = DAG.getNode(ISD::XOR, DL, CarryType, Subc.getValue(1),
17958+
DAG.getAllOnesConstant(DL, CarryType));
17959+
return DAG.getNode(ISD::UADDO_CARRY, DL, VTs, LHS,
17960+
DAG.getConstant(0, DL, MVT::i64), Invert);
17961+
}
1785217962
}
1785317963

1785417964
return SDValue();

‎llvm/lib/Target/PowerPC/PPCISelLowering.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -163,6 +163,7 @@ namespace llvm {
163163
SRL,
164164
SRA,
165165
SHL,
166+
ADDC, ADDE, SUBC, SUBE,
166167

167168
/// FNMSUB - Negated multiply-subtract instruction.
168169
FNMSUB,
@@ -602,6 +603,7 @@ namespace llvm {
602603
/// Loads the entry for GA from the TOC, where the TOC base is given by
603604
/// the last operand.
604605
TOC_ENTRY
606+
605607
};
606608

607609
} // end namespace PPCISD
@@ -1310,6 +1312,8 @@ namespace llvm {
13101312
SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
13111313
SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
13121314
SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
1315+
SDValue LowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) const;
1316+
SDValue LowerADDSUBO(SDValue Op, SelectionDAG &DAG) const;
13131317
SDValue lowerToLibCall(const char *LibCallName, SDValue Op,
13141318
SelectionDAG &DAG) const;
13151319
SDValue lowerLibCallBasedOnType(const char *LibCallFloatName,

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -760,13 +760,13 @@ def STFDXTLS : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:
760760
let isCommutable = 1 in
761761
defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
762762
"addc", "$RT, $RA, $RB", IIC_IntGeneral,
763-
[(set i64:$RT, (addc i64:$RA, i64:$RB))]>,
763+
[(set i64:$RT, (PPCaddc i64:$RA, i64:$RB))]>,
764764
PPC970_DGroup_Cracked;
765765

766766
let Defs = [CARRY] in
767767
def ADDIC8 : DForm_2<12, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
768768
"addic $RST, $RA, $D", IIC_IntGeneral,
769-
[(set i64:$RST, (addc i64:$RA, imm64SExt16:$D))]>;
769+
[(set i64:$RST, (PPCaddc i64:$RA, imm64SExt16:$D))]>;
770770
def ADDI8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),
771771
"addi $RST, $RA, $D", IIC_IntSimple,
772772
[(set i64:$RST, (add i64:$RA, imm64SExt16:$D))]>;
@@ -782,11 +782,11 @@ def LA8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),
782782
let Defs = [CARRY] in {
783783
def SUBFIC8: DForm_2< 8, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
784784
"subfic $RST, $RA, $D", IIC_IntGeneral,
785-
[(set i64:$RST, (subc imm64SExt16:$D, i64:$RA))]>;
785+
[(set i64:$RST, (PPCsubc imm64SExt16:$D, i64:$RA))]>;
786786
}
787787
defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
788788
"subfc", "$RT, $RA, $RB", IIC_IntGeneral,
789-
[(set i64:$RT, (subc i64:$RB, i64:$RA))]>,
789+
[(set i64:$RT, (PPCsubc i64:$RB, i64:$RA))]>,
790790
PPC970_DGroup_Cracked;
791791
defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
792792
"subf", "$RT, $RA, $RB", IIC_IntGeneral,
@@ -798,22 +798,22 @@ let Uses = [CARRY] in {
798798
let isCommutable = 1 in
799799
defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
800800
"adde", "$RT, $RA, $RB", IIC_IntGeneral,
801-
[(set i64:$RT, (adde i64:$RA, i64:$RB))]>;
801+
[(set i64:$RT, (PPCadde i64:$RA, i64:$RB, CARRY))]>;
802802
defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$RT), (ins g8rc:$RA),
803803
"addme", "$RT, $RA", IIC_IntGeneral,
804-
[(set i64:$RT, (adde i64:$RA, -1))]>;
804+
[(set i64:$RT, (PPCadde i64:$RA, -1, CARRY))]>;
805805
defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$RT), (ins g8rc:$RA),
806806
"addze", "$RT, $RA", IIC_IntGeneral,
807-
[(set i64:$RT, (adde i64:$RA, 0))]>;
807+
[(set i64:$RT, (PPCadde i64:$RA, 0, CARRY))]>;
808808
defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
809809
"subfe", "$RT, $RA, $RB", IIC_IntGeneral,
810-
[(set i64:$RT, (sube i64:$RB, i64:$RA))]>;
810+
[(set i64:$RT, (PPCsube i64:$RB, i64:$RA, CARRY))]>;
811811
defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$RT), (ins g8rc:$RA),
812812
"subfme", "$RT, $RA", IIC_IntGeneral,
813-
[(set i64:$RT, (sube -1, i64:$RA))]>;
813+
[(set i64:$RT, (PPCsube -1, i64:$RA, CARRY))]>;
814814
defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$RT), (ins g8rc:$RA),
815815
"subfze", "$RT, $RA", IIC_IntGeneral,
816-
[(set i64:$RT, (sube 0, i64:$RA))]>;
816+
[(set i64:$RT, (PPCsube 0, i64:$RA, CARRY))]>;
817817
}
818818
} // isCodeGenOnly
819819

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 34 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,21 @@ def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [
124124
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
125125
]>;
126126

127+
// RES, CARRY = op LHS, RHS
128+
def SDT_PPCBinaryArithWithFlagsOut : SDTypeProfile<2, 2, [
129+
SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
130+
SDTCisInt<0>,
131+
SDTCisVT<1, i32>,
132+
]>;
133+
134+
// RES, CARRY = op LHS, RHS, CARRY
135+
def SDT_PPCBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, [
136+
SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
137+
SDTCisInt<0>,
138+
SDTCisSameAs<1, 4>,
139+
SDTCisVT<1, i32>,
140+
]>;
141+
127142
//===----------------------------------------------------------------------===//
128143
// PowerPC specific DAG Nodes.
129144
//
@@ -401,6 +416,15 @@ def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR",
401416
def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR",
402417
SDTIntUnaryOp, []>;
403418

419+
def PPCaddc : SDNode<"PPCISD::ADDC", SDT_PPCBinaryArithWithFlagsOut,
420+
[SDNPCommutative]>;
421+
def PPCadde : SDNode<"PPCISD::ADDE", SDT_PPCBinaryArithWithFlagsInOut,
422+
[]>;
423+
def PPCsubc : SDNode<"PPCISD::SUBC", SDT_PPCBinaryArithWithFlagsOut,
424+
[]>;
425+
def PPCsube : SDNode<"PPCISD::SUBE", SDT_PPCBinaryArithWithFlagsInOut,
426+
[]>;
427+
404428
//===----------------------------------------------------------------------===//
405429
// PowerPC specific transformation functions and pattern fragments.
406430
//
@@ -2287,7 +2311,7 @@ let BaseName = "addic" in {
22872311
let Defs = [CARRY] in
22882312
def ADDIC : DForm_2<12, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
22892313
"addic $RST, $RA, $D", IIC_IntGeneral,
2290-
[(set i32:$RST, (addc i32:$RA, imm32SExt16:$D))]>,
2314+
[(set i32:$RST, (PPCaddc i32:$RA, imm32SExt16:$D))]>,
22912315
RecFormRel, PPC970_DGroup_Cracked;
22922316
let Defs = [CARRY, CR0] in
22932317
def ADDIC_rec : DForm_2<13, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
@@ -2308,7 +2332,7 @@ def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
23082332
let Defs = [CARRY] in
23092333
def SUBFIC : DForm_2< 8, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
23102334
"subfic $RST, $RA, $D", IIC_IntGeneral,
2311-
[(set i32:$RST, (subc imm32SExt16:$D, i32:$RA))]>;
2335+
[(set i32:$RST, (PPCsubc imm32SExt16:$D, i32:$RA))]>;
23122336

23132337
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
23142338
def LI : DForm_2_r0<14, (outs gprc:$RST), (ins s16imm:$D),
@@ -2905,7 +2929,7 @@ def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$RT), (ins gprc:$RA, tlsreg32:$RB
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let isCommutable = 1 in
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defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"addc", "$RT, $RA, $RB", IIC_IntGeneral,
2908-
[(set i32:$RT, (addc i32:$RA, i32:$RB))]>,
2932+
[(set i32:$RT, (PPCaddc i32:$RA, i32:$RB))]>,
29092933
PPC970_DGroup_Cracked;
29102934

29112935
defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
@@ -2938,7 +2962,7 @@ defm SUBF : XOForm_1rx<31, 40, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
29382962
[(set i32:$RT, (sub i32:$RB, i32:$RA))]>;
29392963
defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
29402964
"subfc", "$RT, $RA, $RB", IIC_IntGeneral,
2941-
[(set i32:$RT, (subc i32:$RB, i32:$RA))]>,
2965+
[(set i32:$RT, (PPCsubc i32:$RB, i32:$RA))]>,
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PPC970_DGroup_Cracked;
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defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$RT), (ins gprc:$RA),
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"neg", "$RT, $RA", IIC_IntSimple,
@@ -2947,22 +2971,22 @@ let Uses = [CARRY] in {
29472971
let isCommutable = 1 in
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defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"adde", "$RT, $RA, $RB", IIC_IntGeneral,
2950-
[(set i32:$RT, (adde i32:$RA, i32:$RB))]>;
2974+
[(set i32:$RT, (PPCadde i32:$RA, i32:$RB, CARRY))]>;
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defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$RT), (ins gprc:$RA),
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"addme", "$RT, $RA", IIC_IntGeneral,
2953-
[(set i32:$RT, (adde i32:$RA, -1))]>;
2977+
[(set i32:$RT, (PPCadde i32:$RA, -1, CARRY))]>;
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defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$RT), (ins gprc:$RA),
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"addze", "$RT, $RA", IIC_IntGeneral,
2956-
[(set i32:$RT, (adde i32:$RA, 0))]>;
2980+
[(set i32:$RT, (PPCadde i32:$RA, 0, CARRY))]>;
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defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
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"subfe", "$RT, $RA, $RB", IIC_IntGeneral,
2959-
[(set i32:$RT, (sube i32:$RB, i32:$RA))]>;
2983+
[(set i32:$RT, (PPCsube i32:$RB, i32:$RA, CARRY))]>;
29602984
defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$RT), (ins gprc:$RA),
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"subfme", "$RT, $RA", IIC_IntGeneral,
2962-
[(set i32:$RT, (sube -1, i32:$RA))]>;
2986+
[(set i32:$RT, (PPCsube -1, i32:$RA, CARRY))]>;
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defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$RT), (ins gprc:$RA),
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"subfze", "$RT, $RA", IIC_IntGeneral,
2965-
[(set i32:$RT, (sube 0, i32:$RA))]>;
2989+
[(set i32:$RT, (PPCsube 0, i32:$RA, CARRY))]>;
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}
29672991
}
29682992

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