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[RISCV][GlobalISel] Legalize bitshift instructions for narrow types
Legalize G_SHL, G_ASHR and G_LSHR for types narrower and upto (and including) XLen: (i7, i8, i16 and i32) for rv32 and (i8, i15, i16, i32 and i64) for rv64. This requires adding some rules to handle G_ANYEXT, G_ZEXT and G_SEXT. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D155772
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‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

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@@ -29,6 +29,12 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
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.legalFor({XLenLLT})
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.clampScalar(0, XLenLLT, XLenLLT);
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getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
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.legalFor({{XLenLLT, XLenLLT}})
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.widenScalarToNextPow2(0)
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.clampScalar(1, XLenLLT, XLenLLT)
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.clampScalar(0, XLenLLT, XLenLLT);
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// Extensions
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auto ExtLegalFunc = [=](const LegalityQuery &Query) {
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unsigned DstSize = Query.Types[0].getSizeInBits();
@@ -53,6 +59,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
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.legalIf(ExtLegalFunc)
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.clampScalar(0, XLenLLT, XLenLLT);
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getActionDefinitionsBuilder(G_SEXT_INREG).legalFor({XLenLLT}).lower();
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// Merge/Unmerge
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for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
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unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1;

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir

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@@ -0,0 +1,89 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s
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---
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name: ashr_i7
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: ashr_i7
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
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; CHECK-NEXT: $x10 = COPY [[ASHR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s7) = G_TRUNC %0(s32)
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%3:_(s7) = G_TRUNC %1(s32)
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%4:_(s7) = G_ASHR %2, %3
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%5:_(s32) = G_ANYEXT %4(s7)
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$x10 = COPY %5(s32)
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PseudoRET implicit $x10
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...
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---
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name: ashr_i8
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: ashr_i8
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
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; CHECK-NEXT: $x10 = COPY [[ASHR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s8) = G_TRUNC %0(s32)
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%3:_(s8) = G_TRUNC %1(s32)
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%4:_(s8) = G_ASHR %2, %3
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%5:_(s32) = G_ANYEXT %4(s8)
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$x10 = COPY %5(s32)
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PseudoRET implicit $x10
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...
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---
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name: ashr_i16
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: ashr_i16
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
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; CHECK-NEXT: $x10 = COPY [[ASHR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s16) = G_TRUNC %0(s32)
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%3:_(s16) = G_TRUNC %1(s32)
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%4:_(s16) = G_ASHR %2, %3
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%5:_(s32) = G_ANYEXT %4(s16)
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$x10 = COPY %5(s32)
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PseudoRET implicit $x10
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...
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---
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name: ashr_i32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: ashr_i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
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; CHECK-NEXT: $x10 = COPY [[ASHR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s32) = G_ASHR %0, %1
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$x10 = COPY %2(s32)
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PseudoRET implicit $x10
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...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s
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---
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name: lshr_i1
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: lshr_i1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
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; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s1) = G_TRUNC %0(s32)
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%3:_(s1) = G_TRUNC %1(s32)
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%4:_(s1) = G_LSHR %2, %3
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%5:_(s32) = G_ANYEXT %4(s1)
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$x10 = COPY %5(s32)
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PseudoRET implicit $x10
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...
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---
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name: lshr_i8
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: lshr_i8
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
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; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s8) = G_TRUNC %0(s32)
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%3:_(s8) = G_TRUNC %1(s32)
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%4:_(s8) = G_LSHR %2, %3
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%5:_(s32) = G_ANYEXT %4(s8)
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$x10 = COPY %5(s32)
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PseudoRET implicit $x10
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...
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---
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name: lshr_i16
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: lshr_i16
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
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; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s16) = G_TRUNC %0(s32)
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%3:_(s16) = G_TRUNC %1(s32)
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%4:_(s16) = G_LSHR %2, %3
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%5:_(s32) = G_ANYEXT %4(s16)
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$x10 = COPY %5(s32)
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PseudoRET implicit $x10
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...
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---
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name: lshr_i32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: lshr_i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
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; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s32) = G_LSHR %0, %1
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$x10 = COPY %2(s32)
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PseudoRET implicit $x10
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...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir

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@@ -0,0 +1,86 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s
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---
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name: shl_i1
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: shl_i1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
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; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s1) = G_TRUNC %0(s32)
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%3:_(s1) = G_TRUNC %1(s32)
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%4:_(s1) = G_SHL %2, %3
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%5:_(s32) = G_ANYEXT %4(s1)
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$x10 = COPY %5(s32)
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PseudoRET implicit $x10
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...
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---
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name: shl_i8
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: shl_i8
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
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; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s8) = G_TRUNC %0(s32)
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%3:_(s8) = G_TRUNC %1(s32)
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%4:_(s8) = G_SHL %2, %3
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%5:_(s32) = G_ANYEXT %4(s8)
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$x10 = COPY %5(s32)
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PseudoRET implicit $x10
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...
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---
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name: shl_i16
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: shl_i16
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
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; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s16) = G_TRUNC %0(s32)
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%3:_(s16) = G_TRUNC %1(s32)
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%4:_(s16) = G_SHL %2, %3
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%5:_(s32) = G_ANYEXT %4(s16)
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$x10 = COPY %5(s32)
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PseudoRET implicit $x10
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...
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---
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name: shl_i32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: shl_i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
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; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s32) = G_SHL %0, %1
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$x10 = COPY %2(s32)
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PseudoRET implicit $x10
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...

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