@@ -1605,6 +1605,31 @@ define i32 @combine_mul_nabs_i32(i32 %0) {
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ret i32 %m
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}
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+ define i32 @combine_mul_nabs_i32_unsigned_wrap (i32 %0 ) {
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+ ; CHECK-LABEL: @combine_mul_nabs_i32_unsigned_wrap(
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+ ; CHECK-NEXT: [[M:%.*]] = mul i32 [[TMP0:%.*]], [[TMP0]]
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+ ; CHECK-NEXT: ret i32 [[M]]
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+ ;
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+ %c = icmp slt i32 %0 , 0
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+ %s = sub nsw i32 0 , %0
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+ %r = select i1 %c , i32 %0 , i32 %s
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+ %m = mul nuw i32 %r , %r
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+ ret i32 %m
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+ }
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+
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+ define i32 @combine_mul_nabs_i32_signed_wrap (i32 %0 ) {
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+ ; CHECK-LABEL: @combine_mul_nabs_i32_signed_wrap(
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+ ; CHECK-NEXT: [[M:%.*]] = mul i32 [[TMP0:%.*]], [[TMP0]]
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+ ; CHECK-NEXT: ret i32 [[M]]
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+ ;
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+ %c = icmp slt i32 %0 , 0
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+ %s = sub nsw i32 0 , %0
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+ %r = select i1 %c , i32 %0 , i32 %s
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+ %m = mul nsw i32 %r , %r
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+ ret i32 %m
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+ }
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+
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+
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define <4 x i32 > @combine_mul_nabs_v4i32 (<4 x i32 > %0 ) {
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; CHECK-LABEL: @combine_mul_nabs_v4i32(
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; CHECK-NEXT: [[M:%.*]] = mul <4 x i32> [[TMP0:%.*]], [[TMP0]]
@@ -1617,6 +1642,30 @@ define <4 x i32> @combine_mul_nabs_v4i32(<4 x i32> %0) {
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ret <4 x i32 > %m
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}
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+ define <4 x i32 > @combine_mul_nabs_v4i32_unsigned_wrap (<4 x i32 > %0 ) {
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+ ; CHECK-LABEL: @combine_mul_nabs_v4i32_unsigned_wrap(
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+ ; CHECK-NEXT: [[M:%.*]] = mul <4 x i32> [[TMP0:%.*]], [[TMP0]]
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+ ; CHECK-NEXT: ret <4 x i32> [[M]]
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+ ;
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+ %c = icmp slt <4 x i32 > %0 , zeroinitializer
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+ %s = sub nsw <4 x i32 > zeroinitializer , %0
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+ %r = select <4 x i1 > %c , <4 x i32 > %0 , <4 x i32 > %s
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+ %m = mul nuw <4 x i32 > %r , %r
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+ ret <4 x i32 > %m
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+ }
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+
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+ define <4 x i32 > @combine_mul_nabs_v4i32_signed_wrap (<4 x i32 > %0 ) {
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+ ; CHECK-LABEL: @combine_mul_nabs_v4i32_signed_wrap(
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+ ; CHECK-NEXT: [[M:%.*]] = mul <4 x i32> [[TMP0:%.*]], [[TMP0]]
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+ ; CHECK-NEXT: ret <4 x i32> [[M]]
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+ ;
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+ %c = icmp slt <4 x i32 > %0 , zeroinitializer
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+ %s = sub nsw <4 x i32 > zeroinitializer , %0
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+ %r = select <4 x i1 > %c , <4 x i32 > %0 , <4 x i32 > %s
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+ %m = mul nsw <4 x i32 > %r , %r
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+ ret <4 x i32 > %m
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+ }
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+
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define i32 @combine_mul_abs_intrin (i32 %x ) {
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; CHECK-LABEL: @combine_mul_abs_intrin(
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], [[X]]
@@ -1638,6 +1687,28 @@ define i32 @combine_mul_nabs_intrin(i32 %x) {
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ret i32 %mul
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}
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+ define i32 @combine_mul_nabs_intrin_unsigned_flags (i32 %x ) {
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+ ; CHECK-LABEL: @combine_mul_nabs_intrin_unsigned_flags(
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+ ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], [[X]]
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+ ; CHECK-NEXT: ret i32 [[MUL]]
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+ ;
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+ %abs = call i32 @llvm.abs.i32 (i32 %x , i1 false )
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+ %neg = sub i32 0 , %abs
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+ %mul = mul nuw i32 %neg , %neg
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+ ret i32 %mul
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+ }
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+
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+ define i32 @combine_mul_nabs_intrin_signed_flags (i32 %x ) {
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+ ; CHECK-LABEL: @combine_mul_nabs_intrin_signed_flags(
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+ ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], [[X]]
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+ ; CHECK-NEXT: ret i32 [[MUL]]
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+ ;
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+ %abs = call i32 @llvm.abs.i32 (i32 %x , i1 false )
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+ %neg = sub i32 0 , %abs
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+ %mul = mul nsw i32 %neg , %neg
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+ ret i32 %mul
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+ }
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+
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; z * splat(0) = splat(0), even for scalable vectors
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define <vscale x 2 x i64 > @mul_scalable_splat_zero (<vscale x 2 x i64 > %z ) {
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; CHECK-LABEL: @mul_scalable_splat_zero(
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