@@ -50,9 +50,9 @@ static bool isValidRegDefOf(const MachineOperand &MO, MCRegister PhysReg,
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void ReachingDefAnalysis::enterBasicBlock (MachineBasicBlock *MBB) {
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unsigned MBBNumber = MBB->getNumber ();
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- assert (MBBNumber < MBBReachingDefs.size () &&
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+ assert (MBBNumber < MBBReachingDefs.numBlockIDs () &&
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" Unexpected basic block number." );
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- MBBReachingDefs[MBBNumber]. resize ( NumRegUnits);
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+ MBBReachingDefs. startBasicBlock (MBBNumber, NumRegUnits);
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// Reset instruction counter in each basic block.
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CurInstr = 0 ;
@@ -71,7 +71,7 @@ void ReachingDefAnalysis::enterBasicBlock(MachineBasicBlock *MBB) {
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// before the call.
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if (LiveRegs[Unit] != -1 ) {
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LiveRegs[Unit] = -1 ;
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- MBBReachingDefs[MBBNumber][Unit]. push_back ( -1 );
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+ MBBReachingDefs. append (MBBNumber, Unit, -1 );
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}
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}
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}
@@ -97,7 +97,7 @@ void ReachingDefAnalysis::enterBasicBlock(MachineBasicBlock *MBB) {
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// Insert the most recent reaching definition we found.
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for (unsigned Unit = 0 ; Unit != NumRegUnits; ++Unit)
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if (LiveRegs[Unit] != ReachingDefDefaultVal)
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- MBBReachingDefs[MBBNumber][Unit]. push_back ( LiveRegs[Unit]);
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+ MBBReachingDefs. append (MBBNumber, Unit, LiveRegs[Unit]);
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}
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void ReachingDefAnalysis::leaveBasicBlock (MachineBasicBlock *MBB) {
@@ -122,7 +122,7 @@ void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
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assert (!MI->isDebugInstr () && " Won't process debug instructions" );
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unsigned MBBNumber = MI->getParent ()->getNumber ();
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- assert (MBBNumber < MBBReachingDefs.size () &&
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+ assert (MBBNumber < MBBReachingDefs.numBlockIDs () &&
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" Unexpected basic block number." );
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for (auto &MO : MI->operands ()) {
@@ -136,7 +136,7 @@ void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
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// How many instructions since this reg unit was last written?
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if (LiveRegs[Unit] != CurInstr) {
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LiveRegs[Unit] = CurInstr;
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- MBBReachingDefs[MBBNumber][Unit]. push_back ( CurInstr);
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+ MBBReachingDefs. append (MBBNumber, Unit, CurInstr);
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}
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}
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}
@@ -146,7 +146,7 @@ void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
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void ReachingDefAnalysis::reprocessBasicBlock (MachineBasicBlock *MBB) {
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unsigned MBBNumber = MBB->getNumber ();
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- assert (MBBNumber < MBBReachingDefs.size () &&
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+ assert (MBBNumber < MBBReachingDefs.numBlockIDs () &&
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" Unexpected basic block number." );
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// Count number of non-debug instructions for end of block adjustment.
@@ -169,16 +169,16 @@ void ReachingDefAnalysis::reprocessBasicBlock(MachineBasicBlock *MBB) {
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if (Def == ReachingDefDefaultVal)
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continue ;
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- auto Start = MBBReachingDefs[MBBNumber][Unit]. begin ( );
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- if (Start != MBBReachingDefs[MBBNumber][Unit]. end () && *Start < 0 ) {
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- if (*Start >= Def)
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+ auto Defs = MBBReachingDefs. defs (MBBNumber, Unit );
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+ if (!Defs. empty () && Defs. front () < 0 ) {
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+ if (Defs. front () >= Def)
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continue ;
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// Update existing reaching def from predecessor to a more recent one.
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- *Start = Def;
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+ MBBReachingDefs. replaceFront (MBBNumber, Unit, Def) ;
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} else {
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// Insert new reaching def from predecessor.
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- MBBReachingDefs[MBBNumber][Unit]. insert (Start , Def);
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+ MBBReachingDefs. prepend (MBBNumber, Unit , Def);
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}
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// Update reaching def at end of BB. Keep in mind that these are
@@ -234,7 +234,7 @@ void ReachingDefAnalysis::reset() {
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void ReachingDefAnalysis::init () {
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NumRegUnits = TRI->getNumRegUnits ();
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- MBBReachingDefs.resize (MF->getNumBlockIDs ());
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+ MBBReachingDefs.init (MF->getNumBlockIDs ());
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// Initialize the MBBOutRegsInfos
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MBBOutRegsInfos.resize (MF->getNumBlockIDs ());
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LoopTraversal Traversal;
@@ -247,10 +247,11 @@ void ReachingDefAnalysis::traverse() {
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processBasicBlock (TraversedMBB);
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#ifndef NDEBUG
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// Make sure reaching defs are sorted and unique.
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- for (MBBDefsInfo &MBBDefs : MBBReachingDefs) {
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- for (MBBRegUnitDefs &RegUnitDefs : MBBDefs) {
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+ for (unsigned MBBNumber = 0 , NumBlockIDs = MF->getNumBlockIDs ();
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+ MBBNumber != NumBlockIDs; ++MBBNumber) {
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+ for (unsigned Unit = 0 ; Unit != NumRegUnits; ++Unit) {
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int LastDef = ReachingDefDefaultVal;
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- for (int Def : RegUnitDefs ) {
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+ for (int Def : MBBReachingDefs. defs (MBBNumber, Unit) ) {
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assert (Def > LastDef && " Defs must be sorted and unique" );
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LastDef = Def;
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}
@@ -265,11 +266,11 @@ int ReachingDefAnalysis::getReachingDef(MachineInstr *MI,
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int InstId = InstIds.lookup (MI);
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int DefRes = ReachingDefDefaultVal;
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unsigned MBBNumber = MI->getParent ()->getNumber ();
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- assert (MBBNumber < MBBReachingDefs.size () &&
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+ assert (MBBNumber < MBBReachingDefs.numBlockIDs () &&
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" Unexpected basic block number." );
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int LatestDef = ReachingDefDefaultVal;
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for (MCRegUnit Unit : TRI->regunits (PhysReg)) {
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- for (int Def : MBBReachingDefs[ MBBNumber][ Unit] ) {
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+ for (int Def : MBBReachingDefs. defs ( MBBNumber, Unit) ) {
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if (Def >= InstId)
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break ;
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DefRes = Def;
@@ -299,7 +300,8 @@ bool ReachingDefAnalysis::hasSameReachingDef(MachineInstr *A, MachineInstr *B,
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MachineInstr *ReachingDefAnalysis::getInstFromId (MachineBasicBlock *MBB,
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int InstId) const {
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- assert (static_cast <size_t >(MBB->getNumber ()) < MBBReachingDefs.size () &&
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+ assert (static_cast <size_t >(MBB->getNumber ()) <
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+ MBBReachingDefs.numBlockIDs () &&
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" Unexpected basic block number." );
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assert (InstId < static_cast <int >(MBB->size ()) &&
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" Unexpected instruction id." );
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