[AIX] Add -msave-reg-params to save arguments to stack

In PowerPC ABI, a few initial arguments are passed through registers,
but their places in parameter save area are reserved, arguments passed
by memory goes after the reserved location.

For debugging purpose, we may want to save copy of the pass-by-reg
arguments into correct places on stack. The new option achieves by
adding new function level attribute and make argument lowering part
aware of it.

Author: ecnelises

clang/include/clang/Basic/CodeGenOptions.def

@@ -425,6 +425,9 @@ CODEGENOPT(ForceAAPCSBitfieldLoad, 1, 0)
 /// Assume that by-value parameters do not alias any other values.
 CODEGENOPT(PassByValueIsNoAlias, 1, 0)
 
+/// Whether to store register parameters to stack.
+CODEGENOPT(SaveRegParams, 1, 0)
+
 /// Whether to not follow the AAPCS that enforces volatile bit-field access width to be
 /// according to the field declaring type width.
 CODEGENOPT(AAPCSBitfieldWidth, 1, 1)

clang/include/clang/Driver/Options.td

@@ -5040,6 +5040,10 @@ def mspe : Flag<["-"], "mspe">, Group<m_ppc_Features_Group>;
 def mno_spe : Flag<["-"], "mno-spe">, Group<m_ppc_Features_Group>;
 def mefpu2 : Flag<["-"], "mefpu2">, Group<m_ppc_Features_Group>;
 } // let Flags = [TargetSpecific]
+def msave_reg_params : Flag<["-"], "msave-reg-params">, Group<m_Group>,
+  Visibility<[ClangOption, CC1Option]>,
+  HelpText<"Save arguments passed by registers to stack">,
+  MarshallingInfoFlag<CodeGenOpts<"SaveRegParams">>;
 def mabi_EQ_quadword_atomics : Flag<["-"], "mabi=quadword-atomics">,
   Group<m_Group>, Visibility<[ClangOption, CC1Option]>,
   HelpText<"Enable quadword atomics ABI on AIX (AIX PPC64 only). Uses lqarx/stqcx. instructions.">,

clang/lib/CodeGen/CGCall.cpp

@@ -1931,6 +1931,9 @@ static void getTrivialDefaultFunctionAttributes(
     if (CodeGenOpts.NullPointerIsValid)
       FuncAttrs.addAttribute(llvm::Attribute::NullPointerIsValid);
 
+    if (CodeGenOpts.SaveRegParams)
+      FuncAttrs.addAttribute("save-reg-params");
+
     if (LangOpts.getDefaultExceptionMode() == LangOptions::FPE_Ignore)
       FuncAttrs.addAttribute("no-trapping-math", "true");
 

clang/lib/Driver/ToolChains/AIX.cpp

@@ -548,6 +548,9 @@ void AIX::addClangTargetOptions(
                   options::OPT_mtocdata))
     addTocDataOptions(Args, CC1Args, getDriver());
 
+  if (Args.hasArg(options::OPT_msave_reg_params))
+    CC1Args.push_back("-msave-reg-params");
+
   if (Args.hasFlag(options::OPT_fxl_pragma_pack,
                    options::OPT_fno_xl_pragma_pack, true))
     CC1Args.push_back("-fxl-pragma-pack");

clang/test/CodeGen/PowerPC/save-reg-params.c

@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm -o - %s -msave-reg-params | FileCheck -check-prefix=SAVE %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -emit-llvm -o - %s -msave-reg-params | FileCheck -check-prefix=SAVE %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -emit-llvm -o - %s -msave-reg-params | FileCheck -check-prefix=SAVE %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm -o - %s | FileCheck -check-prefix=NOSAVE %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -emit-llvm -o - %s | FileCheck -check-prefix=NOSAVE %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -emit-llvm -o - %s | FileCheck -check-prefix=NOSAVE %s
+
+void bar(int);
+void foo(int x) { bar(x); }
+
+// SAVE: attributes #{{[0-9]+}} = { {{.+}} "save-reg-params" {{.+}} }
+// NOSAVE-NOT: "save-reg-params"···

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

@@ -2496,15 +2496,19 @@ void PPCAIXAsmPrinter::emitTracebackTable() {
 
   uint32_t GPRSaved = 0;
 
-  // X13 is reserved under 64-bit environment.
-  unsigned GPRBegin = Subtarget->isPPC64() ? PPC::X14 : PPC::R13;
-  unsigned GPREnd = Subtarget->isPPC64() ? PPC::X31 : PPC::R31;
-
-  for (unsigned Reg = GPRBegin; Reg <= GPREnd; ++Reg) {
-    if (MRI.isPhysRegModified(Reg)) {
-      GPRSaved = GPREnd - Reg + 1;
-      break;
+  if (FI->getForceGPRSaveCount() < 0) {
+    // X13 is reserved under 64-bit environment.
+    unsigned GPRBegin = Subtarget->isPPC64() ? PPC::X14 : PPC::R13;
+    unsigned GPREnd = Subtarget->isPPC64() ? PPC::X31 : PPC::R31;
+
+    for (unsigned Reg = GPRBegin; Reg <= GPREnd; ++Reg) {
+      if (MRI.isPhysRegModified(Reg)) {
+        GPRSaved = GPREnd - Reg + 1;
+        break;
+      }
     }
+  } else {
+    GPRSaved = FI->getForceGPRSaveCount();
   }
 
   SecondHalfOfMandatoryField |= (GPRSaved << TracebackTable::GPRSavedShift) &

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -7224,6 +7224,8 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
   // Reserve space for the linkage area on the stack.
   const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
   CCInfo.AllocateStack(LinkageSize, Align(PtrByteSize));
+  uint64_t SaveStackPos = CCInfo.getStackSize();
+  bool SaveParams = MF.getFunction().hasFnAttribute("save-reg-params");
   CCInfo.AnalyzeFormalArguments(Ins, CC_AIX);
 
   SmallVector<SDValue, 8> MemOps;
@@ -7242,6 +7244,28 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
     if (VA.isMemLoc() && VA.needsCustom() && ValVT.isFloatingPoint())
       continue;
 
+    if (SaveParams && VA.isRegLoc() && !Flags.isByVal()) {
+      const TargetRegisterClass *RegClass = getRegClassForSVT(
+          LocVT.SimpleTy, IsPPC64, Subtarget.hasP8Vector(), Subtarget.hasVSX());
+      // On PPC64, we need to use std instead of stw for GPR.
+      MVT SaveVT = RegClass == &PPC::G8RCRegClass ? MVT::i64 : LocVT;
+      const Register VReg = MF.addLiveIn(VA.getLocReg(), RegClass);
+      SDValue Parm = DAG.getRegister(VReg, SaveVT);
+      int FI = MFI.CreateFixedObject(SaveVT.getStoreSize(), SaveStackPos, true);
+      SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
+      SDValue StoreReg = DAG.getStore(Chain, dl, Parm, FIN,
+                                      MachinePointerInfo(), Align(PtrByteSize));
+      SaveStackPos = alignTo(SaveStackPos + SaveVT.getStoreSize(), PtrByteSize);
+      MemOps.push_back(StoreReg);
+      Chain = StoreReg;
+    }
+
+    if (SaveParams && (VA.isMemLoc() || Flags.isByVal())) {
+      unsigned StoreSize =
+          Flags.isByVal() ? Flags.getByValSize() : LocVT.getStoreSize();
+      SaveStackPos = alignTo(SaveStackPos + StoreSize, PtrByteSize);
+    }
+
     auto HandleMemLoc = [&]() {
       const unsigned LocSize = LocVT.getStoreSize();
       const unsigned ValSize = ValVT.getStoreSize();
@@ -7454,6 +7478,11 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
   FuncInfo->setMinReservedArea(CallerReservedArea);
 
   if (isVarArg) {
+    // Maximum number of saved GPR in traceback table is 8, for varargs,
+    // assuming eight GPRs matches XL behavior.
+    if (SaveParams)
+      FuncInfo->setForceGPRSaveCount(8);
+
     FuncInfo->setVarArgsFrameIndex(
         MFI.CreateFixedObject(PtrByteSize, CCInfo.getStackSize(), true));
     SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

@@ -150,6 +150,9 @@ class PPCFunctionInfo : public MachineFunctionInfo {
   /// to use SExt/ZExt flags in later optimization.
   std::vector<std::pair<Register, ISD::ArgFlagsTy>> LiveInAttrs;
 
+  /// Set a fixed number of saved GPRs, negative if it's non-fixed.
+  int ForceGPRSaveCount = -1;
+
   /// Flags for aix-shared-lib-tls-model-opt, will be lazily initialized for
   /// each function.
   bool AIXFuncUseTLSIEForLD = false;
@@ -163,6 +166,9 @@ class PPCFunctionInfo : public MachineFunctionInfo {
         const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
       const override;
 
+  int getForceGPRSaveCount() const { return ForceGPRSaveCount; }
+  void setForceGPRSaveCount(int Num) { ForceGPRSaveCount = Num; }
+
   int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
   void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }