@@ -18655,22 +18655,15 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
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Src0 = Builder.CreatePointerBitCastOrAddrSpaceCast(Src0, PTy);
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return Builder.CreateCall(F, { Src0, Src1, Src2, Src3, Src4 });
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}
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- case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
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case AMDGPU::BI__builtin_amdgcn_global_atomic_fmin_f64:
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case AMDGPU::BI__builtin_amdgcn_global_atomic_fmax_f64:
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case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_f64:
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case AMDGPU::BI__builtin_amdgcn_flat_atomic_fmin_f64:
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case AMDGPU::BI__builtin_amdgcn_flat_atomic_fmax_f64:
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- case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_f32:
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- case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16: {
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+ case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_f32: {
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Intrinsic::ID IID;
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llvm::Type *ArgTy = llvm::Type::getDoubleTy(getLLVMContext());
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switch (BuiltinID) {
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- case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
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- ArgTy = llvm::FixedVectorType::get(
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- llvm::Type::getHalfTy(getLLVMContext()), 2);
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- IID = Intrinsic::amdgcn_global_atomic_fadd;
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- break;
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case AMDGPU::BI__builtin_amdgcn_global_atomic_fmin_f64:
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IID = Intrinsic::amdgcn_global_atomic_fmin;
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break;
@@ -18690,11 +18683,6 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
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ArgTy = llvm::Type::getFloatTy(getLLVMContext());
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IID = Intrinsic::amdgcn_flat_atomic_fadd;
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break;
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- case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16:
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- ArgTy = llvm::FixedVectorType::get(
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- llvm::Type::getHalfTy(getLLVMContext()), 2);
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- IID = Intrinsic::amdgcn_flat_atomic_fadd;
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- break;
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}
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llvm::Value *Addr = EmitScalarExpr(E->getArg(0));
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llvm::Value *Val = EmitScalarExpr(E->getArg(1));
@@ -19085,7 +19073,9 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
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case AMDGPU::BI__builtin_amdgcn_ds_atomic_fadd_v2f16:
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case AMDGPU::BI__builtin_amdgcn_ds_atomic_fadd_v2bf16:
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case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f32:
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- case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f64: {
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+ case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f64:
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+ case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
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+ case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16: {
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llvm::AtomicRMWInst::BinOp BinOp;
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switch (BuiltinID) {
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case AMDGPU::BI__builtin_amdgcn_atomic_inc32:
@@ -19103,6 +19093,8 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
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case AMDGPU::BI__builtin_amdgcn_ds_atomic_fadd_v2bf16:
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case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f32:
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case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f64:
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+ case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
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+ case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16:
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BinOp = llvm::AtomicRMWInst::FAdd;
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break;
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}
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