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[RISCV] Add FeatureStdExtI to all CPUs in RISCVProcessors.td. NFC (#88805)
This is currently being implied in RISCVISAInfo.cpp. Make it explicit. I'm planning to move all extension information to RISCVFeatures.td and have tablegen create the tables for RISCVISAInfo.cpp. This requires making the creation of RISCVTargetParserDef.inc in tablegen independent of RISCVISAInfo.cpp. So we need an accurate extension list for CPUs in tablegen.
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‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 25 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,11 +56,13 @@ class RISCVTuneProcessorModel<string n,
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def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
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NoSchedModel,
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[Feature32Bit]>,
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[Feature32Bit,
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FeatureStdExtI]>,
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GenericTuneInfo;
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def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
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NoSchedModel,
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[Feature64Bit]>,
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[Feature64Bit,
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FeatureStdExtI]>,
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GenericTuneInfo;
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// Support generic for compatibility with other targets. The triple will be used
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// to change to the appropriate rv32/rv64 version.
@@ -69,11 +71,13 @@ def : ProcessorModel<"generic", NoSchedModel, []>, GenericTuneInfo;
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def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr]>;
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def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr]>;
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def ROCKET : RISCVTuneProcessorModel<"rocket",
@@ -86,6 +90,7 @@ def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
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def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
@@ -94,6 +99,7 @@ def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
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def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
@@ -103,6 +109,7 @@ def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
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def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
@@ -112,6 +119,7 @@ def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
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def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr,
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FeatureStdExtM,
@@ -121,6 +129,7 @@ def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
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def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
@@ -130,6 +139,7 @@ def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
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def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
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SiFive7Model,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
@@ -140,6 +150,7 @@ def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
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def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
@@ -149,6 +160,7 @@ def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
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def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
@@ -158,6 +170,7 @@ def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
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def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
@@ -168,6 +181,7 @@ def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
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def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
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SiFive7Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
@@ -180,6 +194,7 @@ def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
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def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
@@ -190,6 +205,7 @@ def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
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def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
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SiFive7Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
@@ -200,6 +216,7 @@ def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
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def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
@@ -217,6 +234,7 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
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def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
@@ -247,6 +265,7 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
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def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
@@ -286,6 +305,7 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
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def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
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SyntacoreSCR1Model,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtC],
@@ -294,6 +314,7 @@ def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
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def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
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SyntacoreSCR1Model,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
@@ -303,6 +324,7 @@ def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
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def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr,
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FeatureStdExtZicntr,
@@ -332,6 +354,7 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
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def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
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XiangShanNanHuModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,

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