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[RISCV] Remove R_RISCV_RVC_LUI Relocation (#118714)
This was removed from the ABI in riscv-non-isa/riscv-elf-psabi-doc#398. It is not emitted by LLVM, and seems to have been an internal implementation detail in binutils. This is a follow-up to 26ec5da which removed previous binutils internal relocations when they were removed from the ABI. The LLD implementation was not tested when it was added in https://reviews.llvm.org/D39322
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lld/ELF/Arch/RISCV.cpp

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@@ -267,7 +267,6 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s,
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case R_RISCV_HI20:
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case R_RISCV_LO12_I:
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case R_RISCV_LO12_S:
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case R_RISCV_RVC_LUI:
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return R_ABS;
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case R_RISCV_ADD8:
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case R_RISCV_ADD16:
@@ -373,19 +372,6 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
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return;
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}
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case R_RISCV_RVC_LUI: {
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int64_t imm = SignExtend64(val + 0x800, bits) >> 12;
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checkInt(ctx, loc, imm, 6, rel);
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if (imm == 0) { // `c.lui rd, 0` is illegal, convert to `c.li rd, 0`
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write16le(loc, (read16le(loc) & 0x0F83) | 0x4000);
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} else {
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uint16_t imm17 = extractBits(val + 0x800, 17, 17) << 12;
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uint16_t imm16_12 = extractBits(val + 0x800, 16, 12) << 2;
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write16le(loc, (read16le(loc) & 0xEF83) | imm17 | imm16_12);
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}
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return;
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}
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case R_RISCV_JAL: {
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checkInt(ctx, loc, val, 21, rel);
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checkAlignment(ctx, loc, val, 2, rel);

lld/docs/ReleaseNotes.rst

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@@ -39,6 +39,10 @@ ELF Improvements
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Breaking changes
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----------------
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* Removed support for the (deprecated) `R_RISCV_RVC_LUI` relocation. This
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was a binutils-internal relocation used during relaxation, and was not
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emitted by compilers/assemblers.
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COFF Improvements
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-----------------
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* ``/includeglob`` has been implemented to match the behavior of ``--undefined-glob`` available for ELF.

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

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@@ -45,7 +45,6 @@ ELF_RELOC(R_RISCV_GOT32_PCREL, 41)
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ELF_RELOC(R_RISCV_ALIGN, 43)
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ELF_RELOC(R_RISCV_RVC_BRANCH, 44)
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ELF_RELOC(R_RISCV_RVC_JUMP, 45)
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ELF_RELOC(R_RISCV_RVC_LUI, 46)
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ELF_RELOC(R_RISCV_RELAX, 51)
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ELF_RELOC(R_RISCV_SUB6, 52)
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ELF_RELOC(R_RISCV_SET6, 53)

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