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Dinar TemirbulatovDinar Temirbulatov
Dinar Temirbulatov
authored and
Dinar Temirbulatov
committed
Changes provided by Sander de Smalen <[email protected]>.
1 parent 5731cf1 commit 65d0900

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5 files changed

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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 44 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -17517,62 +17517,56 @@ performVecReduceAddExtCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1751717517
SelectionDAG &DAG = DCI.DAG;
1751817518
auto &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
1751917519
SDValue VecOp = N->getOperand(0).getOperand(0);
17520+
EVT VecOpVT = VecOp.getValueType();
1752017521
SDLoc DL(N);
1752117522

17522-
bool IsScalableType = VecOp.getValueType().isScalableVector();
17523-
std::deque<SDValue> ResultValues;
17524-
ResultValues.push_back(VecOp);
17525-
17526-
// Split the input vectors if not legal.
17527-
while (!TLI.isTypeLegal(ResultValues.front().getValueType())) {
17528-
if (!ResultValues.front()
17529-
.getValueType()
17530-
.getVectorElementCount()
17531-
.isKnownEven())
17532-
return SDValue();
17533-
EVT CurVT = ResultValues.front().getValueType();
17534-
while (true) {
17535-
SDValue Vec = ResultValues.front();
17536-
if (Vec.getValueType() != CurVT)
17537-
break;
17538-
ResultValues.pop_front();
17539-
SDValue Lo, Hi;
17540-
std::tie(Lo, Hi) = DAG.SplitVector(Vec, DL);
17541-
ResultValues.push_back(Lo);
17542-
ResultValues.push_back(Hi);
17543-
}
17523+
// Split the input vectors if not legal, e.g.
17524+
// i32 (vecreduce_add (zext nxv32i8 %op to nxv32i32))
17525+
// ->
17526+
// i32 (add
17527+
// (i32 vecreduce_add (zext nxv16i8 %op.lo to nxv16i32)),
17528+
// (i32 vecreduce_add (zext nxv16i8 %op.hi to nxv16i32)))
17529+
if (TLI.getTypeAction(*DAG.getContext(), VecOpVT) ==
17530+
TargetLowering::TypeSplitVector) {
17531+
SDValue Lo, Hi;
17532+
std::tie(Lo, Hi) = DAG.SplitVector(VecOp, DL);
17533+
unsigned ExtOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17534+
EVT HalfVT = N->getOperand(0).getValueType().getHalfNumVectorElementsVT(
17535+
*DAG.getContext());
17536+
Lo = DAG.getNode(ISD::VECREDUCE_ADD, DL, N->getValueType(0),
17537+
DAG.getNode(ExtOpc, DL, HalfVT, Lo));
17538+
Hi = DAG.getNode(ISD::VECREDUCE_ADD, DL, N->getValueType(0),
17539+
DAG.getNode(ExtOpc, DL, HalfVT, Hi));
17540+
return DAG.getNode(ISD::ADD, DL, N->getValueType(0), Lo, Hi);
1754417541
}
1754517542

17546-
EVT ElemType = N->getValueType(0);
17547-
SmallVector<SDValue, 2> Results;
17548-
if (!IsScalableType &&
17549-
!TLI.useSVEForFixedLengthVectorVT(
17550-
ResultValues[0].getValueType(),
17551-
/*OverrideNEON=*/Subtarget.useSVEForFixedLengthVectors(
17552-
ResultValues[0].getValueType())))
17543+
if (!TLI.isTypeLegal(VecOpVT))
1755317544
return SDValue();
1755417545

17555-
for (SDValue Reg : ResultValues) {
17556-
EVT RdxVT = Reg->getValueType(0);
17557-
SDValue Pg = getPredicateForVector(DAG, DL, RdxVT);
17558-
if (!IsScalableType) {
17559-
EVT ContainerVT = getContainerForFixedLengthVector(DAG, RdxVT);
17560-
Reg = convertToScalableVector(DAG, ContainerVT, Reg);
17561-
}
17562-
SDValue Res =
17563-
DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i64,
17564-
DAG.getConstant(IsSigned ? Intrinsic::aarch64_sve_saddv
17565-
: Intrinsic::aarch64_sve_uaddv,
17566-
DL, MVT::i64),
17567-
Pg, Reg);
17568-
if (ElemType != MVT::i64)
17569-
Res = DAG.getAnyExtOrTrunc(Res, DL, ElemType);
17570-
Results.push_back(Res);
17571-
}
17572-
SDValue ToAdd = Results[0];
17573-
for (unsigned I = 1; I < ResultValues.size(); ++I)
17574-
ToAdd = DAG.getNode(ISD::ADD, DL, ElemType, ToAdd, Results[I]);
17575-
return ToAdd;
17546+
if (VecOpVT.isFixedLengthVector() &&
17547+
!TLI.useSVEForFixedLengthVectorVT(VecOpVT, !Subtarget.isNeonAvailable()))
17548+
return SDValue();
17549+
17550+
// The input type is legal so map VECREDUCE_ADD to UADDV/SADDV, e.g.
17551+
// i32 (vecreduce_add (zext nxv16i8 %op to nxv16i32))
17552+
// ->
17553+
// i32 (UADDV nxv16i8:%op)
17554+
EVT ElemType = N->getValueType(0);
17555+
SDValue Pg = getPredicateForVector(DAG, DL, VecOpVT);
17556+
if (VecOpVT.isFixedLengthVector()) {
17557+
EVT ContainerVT = getContainerForFixedLengthVector(DAG, VecOpVT);
17558+
VecOp = convertToScalableVector(DAG, ContainerVT, VecOp);
17559+
}
17560+
SDValue Res =
17561+
DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i64,
17562+
DAG.getConstant(IsSigned ? Intrinsic::aarch64_sve_saddv
17563+
: Intrinsic::aarch64_sve_uaddv,
17564+
DL, MVT::i64),
17565+
Pg, VecOp);
17566+
if (ElemType != MVT::i64)
17567+
Res = DAG.getAnyExtOrTrunc(Res, DL, ElemType);
17568+
17569+
return Res;
1757617570
}
1757717571

1757817572
// Turn a v8i8/v16i8 extended vecreduce into a udot/sdot and vecreduce

‎llvm/test/CodeGen/AArch64/double_reduct.ll

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -145,11 +145,10 @@ define i16 @add_ext_i16(<16 x i8> %a, <16 x i8> %b) {
145145
define i16 @add_ext_v32i16(<32 x i8> %a, <16 x i8> %b) {
146146
; CHECK-LABEL: add_ext_v32i16:
147147
; CHECK: // %bb.0:
148-
; CHECK-NEXT: uaddl2 v3.8h, v0.16b, v1.16b
149-
; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
150-
; CHECK-NEXT: add v0.8h, v0.8h, v3.8h
151-
; CHECK-NEXT: uadalp v0.8h, v2.16b
152-
; CHECK-NEXT: addv h0, v0.8h
148+
; CHECK-NEXT: uaddlp v1.8h, v1.16b
149+
; CHECK-NEXT: uadalp v1.8h, v0.16b
150+
; CHECK-NEXT: uadalp v1.8h, v2.16b
151+
; CHECK-NEXT: addv h0, v1.8h
153152
; CHECK-NEXT: fmov w0, s0
154153
; CHECK-NEXT: ret
155154
%ae = zext <32 x i8> %a to <32 x i16>

‎llvm/test/CodeGen/AArch64/sve-int-reduce.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -220,17 +220,17 @@ define i32 @uaddv_nxv16i16_nxv16i32(<vscale x 32 x i16> %a) {
220220
; CHECK-LABEL: uaddv_nxv16i16_nxv16i32:
221221
; CHECK: // %bb.0:
222222
; CHECK-NEXT: ptrue p0.h
223+
; CHECK-NEXT: uaddv d3, p0, z3.h
224+
; CHECK-NEXT: uaddv d2, p0, z2.h
223225
; CHECK-NEXT: uaddv d1, p0, z1.h
224226
; CHECK-NEXT: uaddv d0, p0, z0.h
225-
; CHECK-NEXT: uaddv d2, p0, z2.h
226-
; CHECK-NEXT: uaddv d3, p0, z3.h
227-
; CHECK-NEXT: fmov w8, s1
228-
; CHECK-NEXT: fmov w9, s0
229-
; CHECK-NEXT: add w8, w9, w8
227+
; CHECK-NEXT: fmov w8, s3
230228
; CHECK-NEXT: fmov w9, s2
231-
; CHECK-NEXT: add w8, w8, w9
232-
; CHECK-NEXT: fmov w9, s3
233-
; CHECK-NEXT: add w0, w8, w9
229+
; CHECK-NEXT: fmov w10, s1
230+
; CHECK-NEXT: fmov w11, s0
231+
; CHECK-NEXT: add w8, w9, w8
232+
; CHECK-NEXT: add w9, w11, w10
233+
; CHECK-NEXT: add w0, w9, w8
234234
; CHECK-NEXT: ret
235235
%1 = zext <vscale x 32 x i16> %a to <vscale x 32 x i32>
236236
%2 = call i32 @llvm.vector.reduce.add.nxv32i64(<vscale x 32 x i32> %1)
@@ -254,21 +254,21 @@ define i32 @uaddv_nxv32i16_nxv32i32(ptr %a) {
254254
; CHECK-LABEL: uaddv_nxv32i16_nxv32i32:
255255
; CHECK: // %bb.0:
256256
; CHECK-NEXT: ptrue p0.h
257-
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, #1, mul vl]
258-
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0]
259-
; CHECK-NEXT: ld1h { z2.h }, p0/z, [x0, #2, mul vl]
260-
; CHECK-NEXT: ld1h { z3.h }, p0/z, [x0, #3, mul vl]
257+
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, #3, mul vl]
258+
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0, #2, mul vl]
259+
; CHECK-NEXT: ld1h { z2.h }, p0/z, [x0, #1, mul vl]
260+
; CHECK-NEXT: ld1h { z3.h }, p0/z, [x0]
261261
; CHECK-NEXT: uaddv d0, p0, z0.h
262262
; CHECK-NEXT: uaddv d1, p0, z1.h
263263
; CHECK-NEXT: uaddv d2, p0, z2.h
264264
; CHECK-NEXT: uaddv d3, p0, z3.h
265265
; CHECK-NEXT: fmov w8, s0
266266
; CHECK-NEXT: fmov w9, s1
267+
; CHECK-NEXT: fmov w10, s2
268+
; CHECK-NEXT: fmov w11, s3
267269
; CHECK-NEXT: add w8, w9, w8
268-
; CHECK-NEXT: fmov w9, s2
269-
; CHECK-NEXT: add w8, w8, w9
270-
; CHECK-NEXT: fmov w9, s3
271-
; CHECK-NEXT: add w0, w8, w9
270+
; CHECK-NEXT: add w9, w11, w10
271+
; CHECK-NEXT: add w0, w9, w8
272272
; CHECK-NEXT: ret
273273
%1 = load <vscale x 32 x i16>, ptr %a, align 16
274274
%2 = zext <vscale x 32 x i16> %1 to <vscale x 32 x i32>

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -9,14 +9,14 @@ define i32 @reduce_uadd_v16i8(<32 x i8> %a) #0 {
99
; NO_STREAMING-LABEL: reduce_uadd_v16i8:
1010
; NO_STREAMING: // %bb.0:
1111
; NO_STREAMING-NEXT: ushll2 v2.8h, v1.16b, #0
12-
; NO_STREAMING-NEXT: ushll2 v3.8h, v0.16b, #0
1312
; NO_STREAMING-NEXT: ushll v1.8h, v1.8b, #0
13+
; NO_STREAMING-NEXT: ushll2 v3.8h, v0.16b, #0
1414
; NO_STREAMING-NEXT: ushll v0.8h, v0.8b, #0
15-
; NO_STREAMING-NEXT: uaddl2 v4.4s, v3.8h, v2.8h
16-
; NO_STREAMING-NEXT: uaddl v2.4s, v3.4h, v2.4h
17-
; NO_STREAMING-NEXT: uaddl2 v5.4s, v0.8h, v1.8h
18-
; NO_STREAMING-NEXT: uaddl v0.4s, v0.4h, v1.4h
19-
; NO_STREAMING-NEXT: add v1.4s, v5.4s, v4.4s
15+
; NO_STREAMING-NEXT: uaddl2 v4.4s, v1.8h, v2.8h
16+
; NO_STREAMING-NEXT: uaddl v1.4s, v1.4h, v2.4h
17+
; NO_STREAMING-NEXT: uaddl2 v2.4s, v0.8h, v3.8h
18+
; NO_STREAMING-NEXT: uaddl v0.4s, v0.4h, v3.4h
19+
; NO_STREAMING-NEXT: add v1.4s, v1.4s, v4.4s
2020
; NO_STREAMING-NEXT: add v0.4s, v0.4s, v2.4s
2121
; NO_STREAMING-NEXT: add v0.4s, v0.4s, v1.4s
2222
; NO_STREAMING-NEXT: addv s0, v0.4s
@@ -55,14 +55,14 @@ define i32 @reduce_sadd_v16i8(<32 x i8> %a) #0 {
5555
; NO_STREAMING-LABEL: reduce_sadd_v16i8:
5656
; NO_STREAMING: // %bb.0:
5757
; NO_STREAMING-NEXT: sshll2 v2.8h, v1.16b, #0
58-
; NO_STREAMING-NEXT: sshll2 v3.8h, v0.16b, #0
5958
; NO_STREAMING-NEXT: sshll v1.8h, v1.8b, #0
59+
; NO_STREAMING-NEXT: sshll2 v3.8h, v0.16b, #0
6060
; NO_STREAMING-NEXT: sshll v0.8h, v0.8b, #0
61-
; NO_STREAMING-NEXT: saddl2 v4.4s, v3.8h, v2.8h
62-
; NO_STREAMING-NEXT: saddl v2.4s, v3.4h, v2.4h
63-
; NO_STREAMING-NEXT: saddl2 v5.4s, v0.8h, v1.8h
64-
; NO_STREAMING-NEXT: saddl v0.4s, v0.4h, v1.4h
65-
; NO_STREAMING-NEXT: add v1.4s, v5.4s, v4.4s
61+
; NO_STREAMING-NEXT: saddl2 v4.4s, v1.8h, v2.8h
62+
; NO_STREAMING-NEXT: saddl v1.4s, v1.4h, v2.4h
63+
; NO_STREAMING-NEXT: saddl2 v2.4s, v0.8h, v3.8h
64+
; NO_STREAMING-NEXT: saddl v0.4s, v0.4h, v3.4h
65+
; NO_STREAMING-NEXT: add v1.4s, v1.4s, v4.4s
6666
; NO_STREAMING-NEXT: add v0.4s, v0.4s, v2.4s
6767
; NO_STREAMING-NEXT: add v0.4s, v0.4s, v1.4s
6868
; NO_STREAMING-NEXT: addv s0, v0.4s

‎llvm/test/CodeGen/AArch64/vecreduce-add.ll

Lines changed: 24 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1968,10 +1968,9 @@ define i32 @test_udot_v16i8(<16 x i8> %a, <16 x i8> %b) {
19681968
; CHECK-SD-BASE: // %bb.0: // %entry
19691969
; CHECK-SD-BASE-NEXT: umull2 v2.8h, v1.16b, v0.16b
19701970
; CHECK-SD-BASE-NEXT: umull v0.8h, v1.8b, v0.8b
1971-
; CHECK-SD-BASE-NEXT: uaddl2 v1.4s, v0.8h, v2.8h
1972-
; CHECK-SD-BASE-NEXT: uaddl v0.4s, v0.4h, v2.4h
1973-
; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v1.4s
1974-
; CHECK-SD-BASE-NEXT: addv s0, v0.4s
1971+
; CHECK-SD-BASE-NEXT: uaddlp v1.4s, v2.8h
1972+
; CHECK-SD-BASE-NEXT: uadalp v1.4s, v0.8h
1973+
; CHECK-SD-BASE-NEXT: addv s0, v1.4s
19751974
; CHECK-SD-BASE-NEXT: fmov w0, s0
19761975
; CHECK-SD-BASE-NEXT: ret
19771976
;
@@ -2296,10 +2295,9 @@ define i32 @test_sdot_v16i8(<16 x i8> %a, <16 x i8> %b) {
22962295
; CHECK-SD-BASE: // %bb.0: // %entry
22972296
; CHECK-SD-BASE-NEXT: smull2 v2.8h, v1.16b, v0.16b
22982297
; CHECK-SD-BASE-NEXT: smull v0.8h, v1.8b, v0.8b
2299-
; CHECK-SD-BASE-NEXT: saddl2 v1.4s, v0.8h, v2.8h
2300-
; CHECK-SD-BASE-NEXT: saddl v0.4s, v0.4h, v2.4h
2301-
; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v1.4s
2302-
; CHECK-SD-BASE-NEXT: addv s0, v0.4s
2298+
; CHECK-SD-BASE-NEXT: saddlp v1.4s, v2.8h
2299+
; CHECK-SD-BASE-NEXT: sadalp v1.4s, v0.8h
2300+
; CHECK-SD-BASE-NEXT: addv s0, v1.4s
23032301
; CHECK-SD-BASE-NEXT: fmov w0, s0
23042302
; CHECK-SD-BASE-NEXT: ret
23052303
;
@@ -3868,10 +3866,9 @@ entry:
38683866
define i16 @add_v32i8_v32i16_zext(<32 x i8> %x) {
38693867
; CHECK-SD-LABEL: add_v32i8_v32i16_zext:
38703868
; CHECK-SD: // %bb.0: // %entry
3871-
; CHECK-SD-NEXT: uaddl2 v2.8h, v0.16b, v1.16b
3872-
; CHECK-SD-NEXT: uaddl v0.8h, v0.8b, v1.8b
3873-
; CHECK-SD-NEXT: add v0.8h, v0.8h, v2.8h
3874-
; CHECK-SD-NEXT: addv h0, v0.8h
3869+
; CHECK-SD-NEXT: uaddlp v1.8h, v1.16b
3870+
; CHECK-SD-NEXT: uadalp v1.8h, v0.16b
3871+
; CHECK-SD-NEXT: addv h0, v1.8h
38753872
; CHECK-SD-NEXT: fmov w0, s0
38763873
; CHECK-SD-NEXT: ret
38773874
;
@@ -3994,10 +3991,9 @@ entry:
39943991
define i16 @add_v32i8_v32i16_sext(<32 x i8> %x) {
39953992
; CHECK-SD-LABEL: add_v32i8_v32i16_sext:
39963993
; CHECK-SD: // %bb.0: // %entry
3997-
; CHECK-SD-NEXT: saddl2 v2.8h, v0.16b, v1.16b
3998-
; CHECK-SD-NEXT: saddl v0.8h, v0.8b, v1.8b
3999-
; CHECK-SD-NEXT: add v0.8h, v0.8h, v2.8h
4000-
; CHECK-SD-NEXT: addv h0, v0.8h
3994+
; CHECK-SD-NEXT: saddlp v1.8h, v1.16b
3995+
; CHECK-SD-NEXT: sadalp v1.8h, v0.16b
3996+
; CHECK-SD-NEXT: addv h0, v1.8h
40013997
; CHECK-SD-NEXT: fmov w0, s0
40023998
; CHECK-SD-NEXT: ret
40033999
;
@@ -4238,14 +4234,14 @@ define i32 @add_v32i8_v32i32_zext(<32 x i8> %x) {
42384234
; CHECK-SD-BASE-LABEL: add_v32i8_v32i32_zext:
42394235
; CHECK-SD-BASE: // %bb.0: // %entry
42404236
; CHECK-SD-BASE-NEXT: ushll2 v2.8h, v1.16b, #0
4241-
; CHECK-SD-BASE-NEXT: ushll2 v3.8h, v0.16b, #0
42424237
; CHECK-SD-BASE-NEXT: ushll v1.8h, v1.8b, #0
4238+
; CHECK-SD-BASE-NEXT: ushll2 v3.8h, v0.16b, #0
42434239
; CHECK-SD-BASE-NEXT: ushll v0.8h, v0.8b, #0
4244-
; CHECK-SD-BASE-NEXT: uaddl2 v4.4s, v3.8h, v2.8h
4245-
; CHECK-SD-BASE-NEXT: uaddl v2.4s, v3.4h, v2.4h
4246-
; CHECK-SD-BASE-NEXT: uaddl2 v5.4s, v0.8h, v1.8h
4247-
; CHECK-SD-BASE-NEXT: uaddl v0.4s, v0.4h, v1.4h
4248-
; CHECK-SD-BASE-NEXT: add v1.4s, v5.4s, v4.4s
4240+
; CHECK-SD-BASE-NEXT: uaddl2 v4.4s, v1.8h, v2.8h
4241+
; CHECK-SD-BASE-NEXT: uaddl v1.4s, v1.4h, v2.4h
4242+
; CHECK-SD-BASE-NEXT: uaddl2 v2.4s, v0.8h, v3.8h
4243+
; CHECK-SD-BASE-NEXT: uaddl v0.4s, v0.4h, v3.4h
4244+
; CHECK-SD-BASE-NEXT: add v1.4s, v1.4s, v4.4s
42494245
; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v2.4s
42504246
; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v1.4s
42514247
; CHECK-SD-BASE-NEXT: addv s0, v0.4s
@@ -4511,14 +4507,14 @@ define i32 @add_v32i8_v32i32_sext(<32 x i8> %x) {
45114507
; CHECK-SD-BASE-LABEL: add_v32i8_v32i32_sext:
45124508
; CHECK-SD-BASE: // %bb.0: // %entry
45134509
; CHECK-SD-BASE-NEXT: sshll2 v2.8h, v1.16b, #0
4514-
; CHECK-SD-BASE-NEXT: sshll2 v3.8h, v0.16b, #0
45154510
; CHECK-SD-BASE-NEXT: sshll v1.8h, v1.8b, #0
4511+
; CHECK-SD-BASE-NEXT: sshll2 v3.8h, v0.16b, #0
45164512
; CHECK-SD-BASE-NEXT: sshll v0.8h, v0.8b, #0
4517-
; CHECK-SD-BASE-NEXT: saddl2 v4.4s, v3.8h, v2.8h
4518-
; CHECK-SD-BASE-NEXT: saddl v2.4s, v3.4h, v2.4h
4519-
; CHECK-SD-BASE-NEXT: saddl2 v5.4s, v0.8h, v1.8h
4520-
; CHECK-SD-BASE-NEXT: saddl v0.4s, v0.4h, v1.4h
4521-
; CHECK-SD-BASE-NEXT: add v1.4s, v5.4s, v4.4s
4513+
; CHECK-SD-BASE-NEXT: saddl2 v4.4s, v1.8h, v2.8h
4514+
; CHECK-SD-BASE-NEXT: saddl v1.4s, v1.4h, v2.4h
4515+
; CHECK-SD-BASE-NEXT: saddl2 v2.4s, v0.8h, v3.8h
4516+
; CHECK-SD-BASE-NEXT: saddl v0.4s, v0.4h, v3.4h
4517+
; CHECK-SD-BASE-NEXT: add v1.4s, v1.4s, v4.4s
45224518
; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v2.4s
45234519
; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v1.4s
45244520
; CHECK-SD-BASE-NEXT: addv s0, v0.4s

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