@@ -47591,27 +47591,19 @@ static SDValue combineVSelectToBLENDV(SDNode *N, SelectionDAG &DAG,
47591
47591
static SDValue combineLogicBlendIntoConditionalNegate(
47592
47592
EVT VT, SDValue Mask, SDValue X, SDValue Y, const SDLoc &DL,
47593
47593
SelectionDAG &DAG, const X86Subtarget &Subtarget) {
47594
+ using namespace SDPatternMatch;
47594
47595
EVT MaskVT = Mask.getValueType();
47595
47596
assert(MaskVT.isInteger() &&
47596
47597
DAG.ComputeNumSignBits(Mask) == MaskVT.getScalarSizeInBits() &&
47597
47598
"Mask must be zero/all-bits");
47598
47599
47599
- if (X.getValueType() != MaskVT || Y.getValueType() != MaskVT)
47600
- return SDValue();
47601
- if (!DAG.getTargetLoweringInfo().isOperationLegal(ISD::SUB, MaskVT))
47600
+ if (X.getValueType() != MaskVT || Y.getValueType() != MaskVT ||
47601
+ !DAG.getTargetLoweringInfo().isOperationLegal(ISD::SUB, MaskVT))
47602
47602
return SDValue();
47603
47603
47604
- auto IsNegV = [](SDNode *N, SDValue V) {
47605
- return N->getOpcode() == ISD::SUB && N->getOperand(1) == V &&
47606
- ISD::isBuildVectorAllZeros(N->getOperand(0).getNode());
47607
- };
47608
-
47609
47604
SDValue V;
47610
- if (IsNegV(Y.getNode(), X))
47611
- V = X;
47612
- else if (IsNegV(X.getNode(), Y))
47613
- V = Y;
47614
- else
47605
+ if (!sd_match(Y, m_Neg(m_AllOf(m_Specific(X), m_Value(V)))) &&
47606
+ !sd_match(X, m_Neg(m_AllOf(m_Specific(Y), m_Value(V)))))
47615
47607
return SDValue();
47616
47608
47617
47609
SDValue SubOp1 = DAG.getNode(ISD::XOR, DL, MaskVT, V, Mask);
0 commit comments