Skip to content

Commit 6684eb4

Browse files
topperctopperc
committed
[RISCV][GISel] Remove IR section from a couple MIR tests. NFC
1 parent dc4185f commit 6684eb4

File tree

4 files changed

+24
-102
lines changed

4 files changed

+24
-102
lines changed

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir

Lines changed: 6 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -2,25 +2,6 @@
22
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
33
# RUN: | FileCheck %s
44

5-
--- |
6-
define void @load_i8(ptr %addr) { ret void }
7-
define void @load_i16(ptr %addr) { ret void }
8-
define void @load_i32(ptr %addr) { ret void }
9-
define void @zextload_i8(ptr %addr) { ret void }
10-
define void @zextload_i16(ptr %addr) { ret void }
11-
define void @sextload_i8(ptr %addr) { ret void }
12-
define void @sextload_i16(ptr %addr) { ret void }
13-
define void @load_p0(ptr %addr) { ret void }
14-
define void @load_fi_i32() {
15-
%ptr0 = alloca i32
16-
ret void
17-
}
18-
define void @load_fi_gep_i32() {
19-
%ptr0 = alloca [2 x i32]
20-
ret void
21-
}
22-
define void @load_gep_i32(ptr %addr) { ret void }
23-
...
245
---
256
name: load_i8
267
legalized: true
@@ -204,15 +185,15 @@ regBankSelected: true
204185
tracksRegLiveness: true
205186

206187
stack:
207-
- { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }
188+
- { id: 0, offset: 0, size: 4, alignment: 4 }
208189

209190
body: |
210191
bb.0:
211192
; CHECK-LABEL: name: load_fi_i32
212-
; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0.ptr0, 0 :: (load (s32))
193+
; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0, 0 :: (load (s32))
213194
; CHECK-NEXT: $x10 = COPY [[LW]]
214195
; CHECK-NEXT: PseudoRET implicit $x10
215-
%0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
196+
%0:gprb(p0) = G_FRAME_INDEX %stack.0
216197
%1:gprb(s32) = G_LOAD %0(p0) :: (load (s32))
217198
$x10 = COPY %1(s32)
218199
PseudoRET implicit $x10
@@ -225,15 +206,15 @@ regBankSelected: true
225206
tracksRegLiveness: true
226207

227208
stack:
228-
- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 4 }
209+
- { id: 0, offset: 0, size: 8, alignment: 4 }
229210

230211
body: |
231212
bb.0:
232213
; CHECK-LABEL: name: load_fi_gep_i32
233-
; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0.ptr0, 4 :: (load (s32))
214+
; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0, 4 :: (load (s32))
234215
; CHECK-NEXT: $x10 = COPY [[LW]]
235216
; CHECK-NEXT: PseudoRET implicit $x10
236-
%0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
217+
%0:gprb(p0) = G_FRAME_INDEX %stack.0
237218
%1:gprb(s32) = G_CONSTANT i32 4
238219
%2:gprb(p0) = G_PTR_ADD %0(p0), %1(s32)
239220
%3:gprb(s32) = G_LOAD %2(p0) :: (load (s32))

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir

Lines changed: 6 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -2,31 +2,6 @@
22
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
33
# RUN: | FileCheck %s
44

5-
--- |
6-
define void @load_i8_i64(ptr %addr) { ret void }
7-
define void @load_i16_i64(ptr %addr) { ret void }
8-
define void @load_i32_i64(ptr %addr) { ret void }
9-
define void @load_i64_i64(ptr %addr) { ret void }
10-
define void @load_p0(ptr %addr) { ret void }
11-
define void @zextload_i8_i64(ptr %addr) { ret void }
12-
define void @zextload_i16_i64(ptr %addr) { ret void }
13-
define void @zextload_i32_i64(ptr %addr) { ret void }
14-
define void @sextload_i8_i64(ptr %addr) { ret void }
15-
define void @sextload_i16_i64(ptr %addr) { ret void }
16-
define void @sextload_i32_i64(ptr %addr) { ret void }
17-
define void @load_i8_i32(ptr %addr) { ret void }
18-
define void @load_i16_i32(ptr %addr) { ret void }
19-
define void @load_i32_i32(ptr %addr) { ret void }
20-
define void @load_fi_i64() {
21-
%ptr0 = alloca i64
22-
ret void
23-
}
24-
define void @load_fi_gep_i64_i64() {
25-
%ptr0 = alloca [2 x i64]
26-
ret void
27-
}
28-
define void @load_gep_i64_i64(ptr %addr) { ret void }
29-
...
305
---
316
name: load_i8_i64
327
legalized: true
@@ -342,15 +317,15 @@ regBankSelected: true
342317
tracksRegLiveness: true
343318

344319
stack:
345-
- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
320+
- { id: 0, offset: 0, size: 8, alignment: 8 }
346321

347322
body: |
348323
bb.0:
349324
; CHECK-LABEL: name: load_fi_i64
350-
; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0.ptr0, 0 :: (load (s64))
325+
; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0, 0 :: (load (s64))
351326
; CHECK-NEXT: $x10 = COPY [[LD]]
352327
; CHECK-NEXT: PseudoRET implicit $x10
353-
%0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
328+
%0:gprb(p0) = G_FRAME_INDEX %stack.0
354329
%1:gprb(s64) = G_LOAD %0(p0) :: (load (s64))
355330
$x10 = COPY %1(s64)
356331
PseudoRET implicit $x10
@@ -363,15 +338,15 @@ regBankSelected: true
363338
tracksRegLiveness: true
364339

365340
stack:
366-
- { id: 0, name: ptr0, offset: 0, size: 16, alignment: 8 }
341+
- { id: 0, offset: 0, size: 16, alignment: 8 }
367342

368343
body: |
369344
bb.0:
370345
; CHECK-LABEL: name: load_fi_gep_i64_i64
371-
; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0.ptr0, 8 :: (load (s64))
346+
; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0, 8 :: (load (s64))
372347
; CHECK-NEXT: $x10 = COPY [[LD]]
373348
; CHECK-NEXT: PseudoRET implicit $x10
374-
%0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
349+
%0:gprb(p0) = G_FRAME_INDEX %stack.0
375350
%1:gprb(s64) = G_CONSTANT i64 8
376351
%2:gprb(p0) = G_PTR_ADD %0(p0), %1(s64)
377352
%3:gprb(s64) = G_LOAD %2(p0) :: (load (s64))

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir

Lines changed: 6 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -2,21 +2,6 @@
22
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
33
# RUN: | FileCheck %s
44
#
5-
--- |
6-
define void @store_i8(i8 %val, ptr %addr) { ret void }
7-
define void @store_i16(i16 %val, ptr %addr) { ret void }
8-
define void @store_i32(i32 %val, ptr %addr) { ret void }
9-
define void @store_p0(ptr %val, ptr %addr) { ret void }
10-
define void @store_fi_i32(ptr %val) {
11-
%ptr0 = alloca i32
12-
ret void
13-
}
14-
define void @store_fi_gep_i32(ptr %val) {
15-
%ptr0 = alloca [2 x i32]
16-
ret void
17-
}
18-
define void @store_gep_i32(i32 %val, ptr %addr) { ret void }
19-
...
205
---
216
name: store_i8
227
legalized: true
@@ -112,7 +97,7 @@ regBankSelected: true
11297
tracksRegLiveness: true
11398

11499
stack:
115-
- { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }
100+
- { id: 0, offset: 0, size: 4, alignment: 4 }
116101

117102
body: |
118103
bb.0:
@@ -122,10 +107,10 @@ body: |
122107
; CHECK: liveins: $x10
123108
; CHECK-NEXT: {{ $}}
124109
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
125-
; CHECK-NEXT: SW [[COPY]], %stack.0.ptr0, 0 :: (store (s32))
110+
; CHECK-NEXT: SW [[COPY]], %stack.0, 0 :: (store (s32))
126111
; CHECK-NEXT: PseudoRET
127112
%0:gprb(s32) = COPY $x10
128-
%1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
113+
%1:gprb(p0) = G_FRAME_INDEX %stack.0
129114
G_STORE %0(s32), %1(p0) :: (store (s32))
130115
PseudoRET
131116
@@ -137,7 +122,7 @@ regBankSelected: true
137122
tracksRegLiveness: true
138123

139124
stack:
140-
- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 4 }
125+
- { id: 0, offset: 0, size: 8, alignment: 4 }
141126

142127
body: |
143128
bb.0:
@@ -147,10 +132,10 @@ body: |
147132
; CHECK: liveins: $x10
148133
; CHECK-NEXT: {{ $}}
149134
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
150-
; CHECK-NEXT: SW [[COPY]], %stack.0.ptr0, 4 :: (store (s32))
135+
; CHECK-NEXT: SW [[COPY]], %stack.0, 4 :: (store (s32))
151136
; CHECK-NEXT: PseudoRET
152137
%0:gprb(s32) = COPY $x10
153-
%1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
138+
%1:gprb(p0) = G_FRAME_INDEX %stack.0
154139
%2:gprb(s32) = G_CONSTANT i32 4
155140
%3:gprb(p0) = G_PTR_ADD %1(p0), %2(s32)
156141
G_STORE %0(s32), %3(p0) :: (store (s32))

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir

Lines changed: 6 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -2,25 +2,6 @@
22
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
33
# RUN: | FileCheck %s
44

5-
--- |
6-
define void @store_i8_i64(i8 %val, ptr %addr) { ret void }
7-
define void @store_i16_i64(i16 %val, ptr %addr) { ret void }
8-
define void @store_i32_i64(i32 %val, ptr %addr) { ret void }
9-
define void @store_i64_i64(i32 %val, ptr %addr) { ret void }
10-
define void @store_p0(ptr %val, ptr %addr) { ret void }
11-
define void @truncstore_i8_i32(i8 %val, ptr %addr) { ret void }
12-
define void @truncstore_i16_i32(i8 %val, ptr %addr) { ret void }
13-
define void @store_i32_i32(i8 %val, ptr %addr) { ret void }
14-
define void @store_fi_i64_i64(ptr %val) {
15-
%ptr0 = alloca i64
16-
ret void
17-
}
18-
define void @store_fi_gep_i64_i64(ptr %val) {
19-
%ptr0 = alloca [2 x i64]
20-
ret void
21-
}
22-
define void @store_gep_i64_i64(i32 %val, ptr %addr) { ret void }
23-
...
245
---
256
name: store_i8_i64
267
legalized: true
@@ -219,7 +200,7 @@ regBankSelected: true
219200
tracksRegLiveness: true
220201

221202
stack:
222-
- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
203+
- { id: 0, offset: 0, size: 8, alignment: 8 }
223204

224205
body: |
225206
bb.0:
@@ -229,10 +210,10 @@ body: |
229210
; CHECK: liveins: $x10
230211
; CHECK-NEXT: {{ $}}
231212
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
232-
; CHECK-NEXT: SD [[COPY]], %stack.0.ptr0, 0 :: (store (s64))
213+
; CHECK-NEXT: SD [[COPY]], %stack.0, 0 :: (store (s64))
233214
; CHECK-NEXT: PseudoRET
234215
%0:gprb(s64) = COPY $x10
235-
%1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
216+
%1:gprb(p0) = G_FRAME_INDEX %stack.0
236217
G_STORE %0(s64), %1(p0) :: (store (s64))
237218
PseudoRET
238219
@@ -244,7 +225,7 @@ regBankSelected: true
244225
tracksRegLiveness: true
245226

246227
stack:
247-
- { id: 0, name: ptr0, offset: 0, size: 16, alignment: 8 }
228+
- { id: 0, offset: 0, size: 16, alignment: 8 }
248229

249230
body: |
250231
bb.0:
@@ -254,10 +235,10 @@ body: |
254235
; CHECK: liveins: $x10
255236
; CHECK-NEXT: {{ $}}
256237
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
257-
; CHECK-NEXT: SD [[COPY]], %stack.0.ptr0, 8 :: (store (s64))
238+
; CHECK-NEXT: SD [[COPY]], %stack.0, 8 :: (store (s64))
258239
; CHECK-NEXT: PseudoRET
259240
%0:gprb(s64) = COPY $x10
260-
%1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
241+
%1:gprb(p0) = G_FRAME_INDEX %stack.0
261242
%2:gprb(s64) = G_CONSTANT i64 8
262243
%3:gprb(p0) = G_PTR_ADD %1(p0), %2(s64)
263244
G_STORE %0(s64), %3(p0) :: (store (s64))

0 commit comments

Comments
 (0)