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AMDGPU: Custom expand flat cmpxchg which may access private
64-bit flat cmpxchg instructions do not work correctly for scratch addresses, and need to be expanded as non-atomic. Allow custom expansion of cmpxchg in AtomicExpand, as is already the case for atomicrmw.
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-164
lines changed

10 files changed

+1157
-164
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2204,6 +2204,11 @@ class TargetLoweringBase {
22042204
"Generic atomicrmw expansion unimplemented on this target");
22052205
}
22062206

2207+
/// Perform a cmpxchg expansion using a target-specific method.
2208+
virtual void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const {
2209+
llvm_unreachable("Generic cmpxchg expansion unimplemented on this target");
2210+
}
2211+
22072212
/// Perform a bit test atomicrmw using a target-specific intrinsic. This
22082213
/// represents the combined bit test intrinsic which will be lowered at a late
22092214
/// stage by the backend.

‎llvm/include/llvm/Transforms/Utils/LowerAtomic.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,13 @@ class IRBuilderBase;
2323
/// Convert the given Cmpxchg into primitive load and compare.
2424
bool lowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI);
2525

26+
/// Emit IR to implement the given cmpxchg operation on values in registers,
27+
/// returning the new value.
28+
std::pair<Value *, Value *> buildAtomicCmpXchgValue(IRBuilderBase &Builder,
29+
Value *Ptr, Value *Cmp,
30+
Value *Val,
31+
Align Alignment);
32+
2633
/// Convert the given RMWI into primitive load and stores,
2734
/// assuming that doing so is legal. Return true if the lowering
2835
/// succeeds.

‎llvm/lib/CodeGen/AtomicExpandPass.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1674,6 +1674,10 @@ bool AtomicExpandImpl::tryExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) {
16741674
return true;
16751675
case TargetLoweringBase::AtomicExpansionKind::NotAtomic:
16761676
return lowerAtomicCmpXchgInst(CI);
1677+
case TargetLoweringBase::AtomicExpansionKind::Expand: {
1678+
TLI->emitExpandAtomicCmpXchg(CI);
1679+
return true;
1680+
}
16771681
}
16781682
}
16791683

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 95 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -16595,9 +16595,21 @@ SITargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1659516595

1659616596
TargetLowering::AtomicExpansionKind
1659716597
SITargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CmpX) const {
16598-
return CmpX->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS
16599-
? AtomicExpansionKind::NotAtomic
16600-
: AtomicExpansionKind::None;
16598+
unsigned AddrSpace = CmpX->getPointerAddressSpace();
16599+
if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS)
16600+
return AtomicExpansionKind::NotAtomic;
16601+
16602+
if (AddrSpace != AMDGPUAS::FLAT_ADDRESS || !flatInstrMayAccessPrivate(CmpX))
16603+
return AtomicExpansionKind::None;
16604+
16605+
const DataLayout &DL = CmpX->getDataLayout();
16606+
16607+
Type *ValTy = CmpX->getNewValOperand()->getType();
16608+
16609+
// If a 64-bit flat atomic may alias private, we need to avoid using the
16610+
// atomic in the private case.
16611+
return DL.getTypeSizeInBits(ValTy) == 64 ? AtomicExpansionKind::Expand
16612+
: AtomicExpansionKind::None;
1660116613
}
1660216614

1660316615
const TargetRegisterClass *
@@ -16761,40 +16773,8 @@ bool SITargetLowering::checkForPhysRegDependency(
1676116773
return false;
1676216774
}
1676316775

16764-
void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
16765-
AtomicRMWInst::BinOp Op = AI->getOperation();
16766-
16767-
if (Op == AtomicRMWInst::Sub || Op == AtomicRMWInst::Or ||
16768-
Op == AtomicRMWInst::Xor) {
16769-
if (auto *ConstVal = dyn_cast<Constant>(AI->getValOperand());
16770-
ConstVal && ConstVal->isNullValue()) {
16771-
// atomicrmw or %ptr, 0 -> atomicrmw add %ptr, 0
16772-
AI->setOperation(AtomicRMWInst::Add);
16773-
16774-
// TODO: Turn the below private handling into a no-op for idempotent
16775-
// cases.
16776-
}
16777-
}
16778-
16779-
// The non-flat expansions should only perform the de-canonicalization of
16780-
// identity values.
16781-
if (AI->getPointerAddressSpace() != AMDGPUAS::FLAT_ADDRESS)
16782-
return;
16783-
16784-
// FullFlatEmulation is true if we need to issue the private, shared, and
16785-
// global cases.
16786-
//
16787-
// If this is false, we are only dealing with the flat-targeting-private case,
16788-
// where we only insert a check for private and still use the flat instruction
16789-
// for global and shared.
16790-
16791-
// TODO: Avoid the private check for the fadd case depending on
16792-
// noalias.addrspace.
16793-
16794-
bool FullFlatEmulation = Op == AtomicRMWInst::FAdd &&
16795-
Subtarget->hasAtomicFaddInsts() &&
16796-
AI->getType()->isFloatTy();
16797-
16776+
void SITargetLowering::emitExpandAtomicAddrSpacePredicate(
16777+
Instruction *AI) const {
1679816778
// Given: atomicrmw fadd ptr %addr, float %val ordering
1679916779
//
1680016780
// With this expansion we produce the following code:
@@ -16841,6 +16821,34 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1684116821
IRBuilder<> Builder(AI);
1684216822
LLVMContext &Ctx = Builder.getContext();
1684316823

16824+
auto *RMW = dyn_cast<AtomicRMWInst>(AI);
16825+
const unsigned PtrOpIdx = RMW ? AtomicRMWInst::getPointerOperandIndex()
16826+
: AtomicCmpXchgInst::getPointerOperandIndex();
16827+
Value *Addr = AI->getOperand(PtrOpIdx);
16828+
16829+
/// TODO: Only need to check private, then emit flat-known-not private (no
16830+
/// need for shared block, or cast to global).
16831+
AtomicCmpXchgInst *CX = dyn_cast<AtomicCmpXchgInst>(AI);
16832+
16833+
Align Alignment;
16834+
if (RMW)
16835+
Alignment = RMW->getAlign();
16836+
else if (CX)
16837+
Alignment = CX->getAlign();
16838+
else
16839+
llvm_unreachable("unhandled atomic operation");
16840+
16841+
// FullFlatEmulation is true if we need to issue the private, shared, and
16842+
// global cases.
16843+
//
16844+
// If this is false, we are only dealing with the flat-targeting-private case,
16845+
// where we only insert a check for private and still use the flat instruction
16846+
// for global and shared.
16847+
16848+
bool FullFlatEmulation = RMW && RMW->getOperation() == AtomicRMWInst::FAdd &&
16849+
Subtarget->hasAtomicFaddInsts() &&
16850+
RMW->getType()->isFloatTy();
16851+
1684416852
// If the return value isn't used, do not introduce a false use in the phi.
1684516853
bool ReturnValueIsUsed = !AI->use_empty();
1684616854

@@ -16862,11 +16870,6 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1686216870
BasicBlock *GlobalBB = BasicBlock::Create(Ctx, "atomicrmw.global", F, ExitBB);
1686316871
BasicBlock *PhiBB = BasicBlock::Create(Ctx, "atomicrmw.phi", F, ExitBB);
1686416872

16865-
Value *Val = AI->getValOperand();
16866-
Type *ValTy = Val->getType();
16867-
Value *Addr = AI->getPointerOperand();
16868-
Align Alignment = AI->getAlign();
16869-
1687016873
std::prev(BB->end())->eraseFromParent();
1687116874
Builder.SetInsertPoint(BB);
1687216875

@@ -16881,8 +16884,7 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1688116884

1688216885
Instruction *Clone = AI->clone();
1688316886
Clone->insertInto(SharedBB, SharedBB->end());
16884-
Clone->getOperandUse(AtomicRMWInst::getPointerOperandIndex())
16885-
.set(CastToLocal);
16887+
Clone->getOperandUse(PtrOpIdx).set(CastToLocal);
1688616888
LoadedShared = Clone;
1688716889

1688816890
Builder.CreateBr(PhiBB);
@@ -16894,14 +16896,29 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1689416896
Builder.CreateCondBr(IsPrivate, PrivateBB, GlobalBB);
1689516897

1689616898
Builder.SetInsertPoint(PrivateBB);
16899+
1689716900
Value *CastToPrivate = Builder.CreateAddrSpaceCast(
1689816901
Addr, PointerType::get(Ctx, AMDGPUAS::PRIVATE_ADDRESS));
16899-
Value *LoadedPrivate = Builder.CreateAlignedLoad(ValTy, CastToPrivate,
16900-
Alignment, "loaded.private");
1690116902

16902-
Value *NewVal = buildAtomicRMWValue(Op, Builder, LoadedPrivate, Val);
16903+
Value *LoadedPrivate;
16904+
if (RMW) {
16905+
LoadedPrivate = Builder.CreateAlignedLoad(
16906+
RMW->getType(), CastToPrivate, RMW->getAlign(), "loaded.private");
16907+
16908+
Value *NewVal = buildAtomicRMWValue(RMW->getOperation(), Builder,
16909+
LoadedPrivate, RMW->getValOperand());
16910+
16911+
Builder.CreateAlignedStore(NewVal, CastToPrivate, RMW->getAlign());
16912+
} else {
16913+
auto [ResultLoad, Equal] =
16914+
buildAtomicCmpXchgValue(Builder, CastToPrivate, CX->getCompareOperand(),
16915+
CX->getNewValOperand(), CX->getAlign());
16916+
16917+
Value *Insert = Builder.CreateInsertValue(PoisonValue::get(CX->getType()),
16918+
ResultLoad, 0);
16919+
LoadedPrivate = Builder.CreateInsertValue(Insert, Equal, 1);
16920+
}
1690316921

16904-
Builder.CreateAlignedStore(NewVal, CastToPrivate, Alignment);
1690516922
Builder.CreateBr(PhiBB);
1690616923

1690716924
Builder.SetInsertPoint(GlobalBB);
@@ -16911,8 +16928,7 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1691116928
if (FullFlatEmulation) {
1691216929
Value *CastToGlobal = Builder.CreateAddrSpaceCast(
1691316930
Addr, PointerType::get(Ctx, AMDGPUAS::GLOBAL_ADDRESS));
16914-
AI->getOperandUse(AtomicRMWInst::getPointerOperandIndex())
16915-
.set(CastToGlobal);
16931+
AI->getOperandUse(PtrOpIdx).set(CastToGlobal);
1691616932
}
1691716933

1691816934
AI->removeFromParent();
@@ -16936,7 +16952,7 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1693616952
Builder.SetInsertPoint(PhiBB);
1693716953

1693816954
if (ReturnValueIsUsed) {
16939-
PHINode *Loaded = Builder.CreatePHI(ValTy, 3);
16955+
PHINode *Loaded = Builder.CreatePHI(AI->getType(), 3);
1694016956
AI->replaceAllUsesWith(Loaded);
1694116957
if (FullFlatEmulation)
1694216958
Loaded->addIncoming(LoadedShared, SharedBB);
@@ -16948,6 +16964,34 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1694816964
Builder.CreateBr(ExitBB);
1694916965
}
1695016966

16967+
void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
16968+
AtomicRMWInst::BinOp Op = AI->getOperation();
16969+
16970+
if (Op == AtomicRMWInst::Sub || Op == AtomicRMWInst::Or ||
16971+
Op == AtomicRMWInst::Xor) {
16972+
if (const auto *ConstVal = dyn_cast<Constant>(AI->getValOperand());
16973+
ConstVal && ConstVal->isNullValue()) {
16974+
// atomicrmw or %ptr, 0 -> atomicrmw add %ptr, 0
16975+
AI->setOperation(AtomicRMWInst::Add);
16976+
16977+
// We may still need the private-alias-flat handling below.
16978+
16979+
// TODO: Skip this for cases where we cannot access remote memory.
16980+
}
16981+
}
16982+
16983+
// The non-flat expansions should only perform the de-canonicalization of
16984+
// identity values.
16985+
if (AI->getPointerAddressSpace() != AMDGPUAS::FLAT_ADDRESS)
16986+
return;
16987+
16988+
emitExpandAtomicAddrSpacePredicate(AI);
16989+
}
16990+
16991+
void SITargetLowering::emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const {
16992+
emitExpandAtomicAddrSpacePredicate(CI);
16993+
}
16994+
1695116995
LoadInst *
1695216996
SITargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
1695316997
IRBuilder<> Builder(AI);

‎llvm/lib/Target/AMDGPU/SIISelLowering.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -544,7 +544,10 @@ class SITargetLowering final : public AMDGPUTargetLowering {
544544
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
545545
AtomicExpansionKind
546546
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
547+
548+
void emitExpandAtomicAddrSpacePredicate(Instruction *AI) const;
547549
void emitExpandAtomicRMW(AtomicRMWInst *AI) const override;
550+
void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const override;
548551

549552
LoadInst *
550553
lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;

‎llvm/lib/Transforms/Utils/LowerAtomic.cpp

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -25,20 +25,29 @@ bool llvm::lowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI) {
2525
Value *Cmp = CXI->getCompareOperand();
2626
Value *Val = CXI->getNewValOperand();
2727

28-
LoadInst *Orig =
29-
Builder.CreateAlignedLoad(Val->getType(), Ptr, CXI->getAlign());
30-
Value *Equal = Builder.CreateICmpEQ(Orig, Cmp);
31-
Value *Res = Builder.CreateSelect(Equal, Val, Orig);
32-
Builder.CreateAlignedStore(Res, Ptr, CXI->getAlign());
28+
auto [Orig, Equal] =
29+
buildAtomicCmpXchgValue(Builder, Ptr, Cmp, Val, CXI->getAlign());
3330

34-
Res = Builder.CreateInsertValue(PoisonValue::get(CXI->getType()), Orig, 0);
31+
Value *Res =
32+
Builder.CreateInsertValue(PoisonValue::get(CXI->getType()), Orig, 0);
3533
Res = Builder.CreateInsertValue(Res, Equal, 1);
3634

3735
CXI->replaceAllUsesWith(Res);
3836
CXI->eraseFromParent();
3937
return true;
4038
}
4139

40+
std::pair<Value *, Value *>
41+
llvm::buildAtomicCmpXchgValue(IRBuilderBase &Builder, Value *Ptr, Value *Cmp,
42+
Value *Val, Align Alignment) {
43+
LoadInst *Orig = Builder.CreateAlignedLoad(Val->getType(), Ptr, Alignment);
44+
Value *Equal = Builder.CreateICmpEQ(Orig, Cmp);
45+
Value *Res = Builder.CreateSelect(Equal, Val, Orig);
46+
Builder.CreateAlignedStore(Res, Ptr, Alignment);
47+
48+
return {Orig, Equal};
49+
}
50+
4251
Value *llvm::buildAtomicRMWValue(AtomicRMWInst::BinOp Op,
4352
IRBuilderBase &Builder, Value *Loaded,
4453
Value *Val) {

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