Skip to content

Commit 6735c5e

Browse files
V-FEXrtinbelicpow2clk
authored
[HLSL] Implement WaveActiveAnyTrue intrinsic (#115902)
Resolves #99160 - [x] Implement `WaveActiveAnyTrue` clang builtin, - [x] Link `WaveActiveAnyTrue` clang builtin with `hlsl_intrinsics.h` - [x] Add sema checks for `WaveActiveAnyTrue` to `CheckHLSLBuiltinFunctionCall` in `SemaChecking.cpp` - [x] Add codegen for `WaveActiveAnyTrue` to `EmitHLSLBuiltinExpr` in `CGBuiltin.cpp` - [x] Add codegen tests to `clang/test/CodeGenHLSL/builtins/WaveActiveAnyTrue.hlsl` - [x] Add sema tests to `clang/test/SemaHLSL/BuiltIns/WaveActiveAnyTrue-errors.hlsl` - [x] Create the `int_dx_WaveActiveAnyTrue` intrinsic in `IntrinsicsDirectX.td` - [x] Create the `DXILOpMapping` of `int_dx_WaveActiveAnyTrue` to `113` in `DXIL.td` - [x] Create the `WaveActiveAnyTrue.ll` and `WaveActiveAnyTrue_errors.ll` tests in `llvm/test/CodeGen/DirectX/` - [x] Create the `int_spv_WaveActiveAnyTrue` intrinsic in `IntrinsicsSPIRV.td` - [x] In SPIRVInstructionSelector.cpp create the `WaveActiveAnyTrue` lowering and map it to `int_spv_WaveActiveAnyTrue` in `SPIRVInstructionSelector::selectIntrinsic`. - [x] Create SPIR-V backend test case in `llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveAnyTrue.ll` --------- Co-authored-by: Finn Plummer <[email protected]> Co-authored-by: Greg Roth <[email protected]>
1 parent cdd1e27 commit 6735c5e

File tree

13 files changed

+146
-51
lines changed

13 files changed

+146
-51
lines changed

‎clang/include/clang/Basic/Builtins.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4750,6 +4750,12 @@ def HLSLAny : LangBuiltin<"HLSL_LANG"> {
47504750
let Prototype = "bool(...)";
47514751
}
47524752

4753+
def HLSLWaveActiveAnyTrue : LangBuiltin<"HLSL_LANG"> {
4754+
let Spellings = ["__builtin_hlsl_wave_active_any_true"];
4755+
let Attributes = [NoThrow, Const];
4756+
let Prototype = "bool(bool)";
4757+
}
4758+
47534759
def HLSLWaveActiveCountBits : LangBuiltin<"HLSL_LANG"> {
47544760
let Spellings = ["__builtin_hlsl_wave_active_count_bits"];
47554761
let Attributes = [NoThrow, Const];

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19282,6 +19282,16 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
1928219282
/*ReturnType=*/Op0->getType(), CGM.getHLSLRuntime().getStepIntrinsic(),
1928319283
ArrayRef<Value *>{Op0, Op1}, nullptr, "hlsl.step");
1928419284
}
19285+
case Builtin::BI__builtin_hlsl_wave_active_any_true: {
19286+
Value *Op = EmitScalarExpr(E->getArg(0));
19287+
llvm::Type *Ty = Op->getType();
19288+
assert(Ty->isIntegerTy(1) &&
19289+
"Intrinsic WaveActiveAnyTrue operand must be a bool");
19290+
19291+
Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveActiveAnyTrueIntrinsic();
19292+
return EmitRuntimeCall(
19293+
Intrinsic::getOrInsertDeclaration(&CGM.getModule(), ID), {Op});
19294+
}
1928519295
case Builtin::BI__builtin_hlsl_wave_active_count_bits: {
1928619296
Value *OpExpr = EmitScalarExpr(E->getArg(0));
1928719297
Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveActiveCountBitsIntrinsic();

‎clang/lib/CodeGen/CGHLSLRuntime.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,7 @@ class CGHLSLRuntime {
9191
GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
9292
GENERATE_HLSL_INTRINSIC_FUNCTION(Dot4AddI8Packed, dot4add_i8packed)
9393
GENERATE_HLSL_INTRINSIC_FUNCTION(Dot4AddU8Packed, dot4add_u8packed)
94+
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveAnyTrue, wave_any)
9495
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveCountBits, wave_active_countbits)
9596
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
9697
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, wave_readlane)

‎clang/lib/Headers/hlsl/hlsl_intrinsics.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2223,6 +2223,15 @@ float4 trunc(float4);
22232223
// Wave* builtins
22242224
//===----------------------------------------------------------------------===//
22252225

2226+
/// \brief Returns true if the expression is true in any active lane in the
2227+
/// current wave.
2228+
///
2229+
/// \param Val The boolean expression to evaluate.
2230+
/// \return True if the expression is true in any lane.
2231+
_HLSL_AVAILABILITY(shadermodel, 6.0)
2232+
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_any_true)
2233+
__attribute__((convergent)) bool WaveActiveAnyTrue(bool Val);
2234+
22262235
/// \brief Counts the number of boolean variables which evaluate to true across
22272236
/// all active lanes in the current wave.
22282237
///

‎clang/test/CodeGenHLSL/builtins/WaveActiveAnyTrue.hlsl

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
// RUN: %clang_cc1 -finclude-default-header -fnative-half-type -triple \
2+
// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \
3+
// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
4+
// RUN: %clang_cc1 -finclude-default-header -fnative-half-type -triple \
5+
// RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \
6+
// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV
7+
8+
// Test basic lowering to runtime function call for int values.
9+
10+
// CHECK-LABEL: define {{.*}}test
11+
bool test(bool p1) {
12+
// CHECK-SPIRV: %[[#entry_tok0:]] = call token @llvm.experimental.convergence.entry()
13+
// CHECK-SPIRV: %[[RET:.*]] = call spir_func i1 @llvm.spv.wave.any(i1 %{{[a-zA-Z0-9]+}}) [ "convergencectrl"(token %[[#entry_tok0]]) ]
14+
// CHECK-DXIL: %[[RET:.*]] = call i1 @llvm.dx.wave.any(i1 %{{[a-zA-Z0-9]+}})
15+
// CHECK: ret i1 %[[RET]]
16+
return WaveActiveAnyTrue(p1);
17+
}

‎clang/test/SemaHLSL/BuiltIns/WaveActiveAnyTrue-errors.hlsl

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -emit-llvm-only -disable-llvm-passes -verify
2+
3+
bool test_too_few_arg() {
4+
return __builtin_hlsl_wave_active_any_true();
5+
// expected-error@-1 {{too few arguments to function call, expected 1, have 0}}
6+
}
7+
8+
bool test_too_many_arg(bool p0) {
9+
return __builtin_hlsl_wave_active_any_true(p0, p0);
10+
// expected-error@-1 {{too many arguments to function call, expected 1, have 2}}
11+
}
12+
13+
struct Foo
14+
{
15+
int a;
16+
};
17+
18+
bool test_type_check(Foo p0) {
19+
return __builtin_hlsl_wave_active_any_true(p0);
20+
// expected-error@-1 {{no viable conversion from 'Foo' to 'bool'}}
21+
}

‎llvm/include/llvm/IR/IntrinsicsDirectX.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLV
9494
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
9595
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
9696
def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
97+
def int_dx_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
9798
def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrConvergent, IntrNoMem]>;
9899
def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
99100
def int_dx_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;

‎llvm/include/llvm/IR/IntrinsicsSPIRV.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
8686
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
8787
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
8888
def int_spv_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
89+
def int_spv_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
8990
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
9091
def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
9192
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;

‎llvm/lib/Target/DirectX/DXIL.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -861,6 +861,14 @@ def CreateHandleFromBinding : DXILOp<217, createHandleFromBinding> {
861861
let stages = [Stages<DXIL1_6, [all_stages]>];
862862
}
863863

864+
def WaveActiveAnyTrue : DXILOp<113, waveAnyTrue> {
865+
let Doc = "returns true if the expression is true in any of the active lanes in the current wave";
866+
let LLVMIntrinsic = int_dx_wave_any;
867+
let arguments = [Int1Ty];
868+
let result = Int1Ty;
869+
let stages = [Stages<DXIL1_0, [all_stages]>];
870+
}
871+
864872
def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
865873
let Doc = "returns 1 for the first lane in the wave";
866874
let LLVMIntrinsic = int_dx_wave_is_first_lane;

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 32 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -257,12 +257,12 @@ class SPIRVInstructionSelector : public InstructionSelector {
257257
bool selectSpvThreadId(Register ResVReg, const SPIRVType *ResType,
258258
MachineInstr &I) const;
259259

260+
bool selectWaveOpInst(Register ResVReg, const SPIRVType *ResType,
261+
MachineInstr &I, unsigned Opcode) const;
262+
260263
bool selectWaveActiveCountBits(Register ResVReg, const SPIRVType *ResType,
261264
MachineInstr &I) const;
262265

263-
bool selectWaveReadLaneAt(Register ResVReg, const SPIRVType *ResType,
264-
MachineInstr &I) const;
265-
266266
bool selectUnmergeValues(MachineInstr &I) const;
267267

268268
bool selectHandleFromBinding(Register &ResVReg, const SPIRVType *ResType,
@@ -1939,24 +1939,36 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg,
19391939
return Result;
19401940
}
19411941

1942+
bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg,
1943+
const SPIRVType *ResType,
1944+
MachineInstr &I,
1945+
unsigned Opcode) const {
1946+
MachineBasicBlock &BB = *I.getParent();
1947+
SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
1948+
1949+
auto BMI = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
1950+
.addDef(ResVReg)
1951+
.addUse(GR.getSPIRVTypeID(ResType))
1952+
.addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I,
1953+
IntTy, TII));
1954+
1955+
for (unsigned J = 2; J < I.getNumOperands(); J++) {
1956+
BMI.addUse(I.getOperand(J).getReg());
1957+
}
1958+
1959+
return BMI.constrainAllUses(TII, TRI, RBI);
1960+
}
1961+
19421962
bool SPIRVInstructionSelector::selectWaveActiveCountBits(
19431963
Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
1944-
assert(I.getNumOperands() == 3);
1945-
assert(I.getOperand(2).isReg());
1946-
MachineBasicBlock &BB = *I.getParent();
19471964

19481965
SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
19491966
SPIRVType *BallotType = GR.getOrCreateSPIRVVectorType(IntTy, 4, I, TII);
19501967
Register BallotReg = MRI->createVirtualRegister(GR.getRegClass(BallotType));
1968+
bool Result = selectWaveOpInst(BallotReg, BallotType, I,
1969+
SPIRV::OpGroupNonUniformBallot);
19511970

1952-
bool Result =
1953-
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpGroupNonUniformBallot))
1954-
.addDef(BallotReg)
1955-
.addUse(GR.getSPIRVTypeID(BallotType))
1956-
.addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII))
1957-
.addUse(I.getOperand(2).getReg())
1958-
.constrainAllUses(TII, TRI, RBI);
1959-
1971+
MachineBasicBlock &BB = *I.getParent();
19601972
Result &=
19611973
BuildMI(BB, I, I.getDebugLoc(),
19621974
TII.get(SPIRV::OpGroupNonUniformBallotBitCount))
@@ -1970,26 +1982,6 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits(
19701982
return Result;
19711983
}
19721984

1973-
bool SPIRVInstructionSelector::selectWaveReadLaneAt(Register ResVReg,
1974-
const SPIRVType *ResType,
1975-
MachineInstr &I) const {
1976-
assert(I.getNumOperands() == 4);
1977-
assert(I.getOperand(2).isReg());
1978-
assert(I.getOperand(3).isReg());
1979-
MachineBasicBlock &BB = *I.getParent();
1980-
1981-
// IntTy is used to define the execution scope, set to 3 to denote a
1982-
// cross-lane interaction equivalent to a SPIR-V subgroup.
1983-
SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
1984-
return BuildMI(BB, I, I.getDebugLoc(),
1985-
TII.get(SPIRV::OpGroupNonUniformShuffle))
1986-
.addDef(ResVReg)
1987-
.addUse(GR.getSPIRVTypeID(ResType))
1988-
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII))
1989-
.addUse(I.getOperand(2).getReg())
1990-
.addUse(I.getOperand(3).getReg());
1991-
}
1992-
19931985
bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
19941986
const SPIRVType *ResType,
19951987
MachineInstr &I) const {
@@ -2838,16 +2830,13 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
28382830
return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
28392831
case Intrinsic::spv_wave_active_countbits:
28402832
return selectWaveActiveCountBits(ResVReg, ResType, I);
2841-
case Intrinsic::spv_wave_is_first_lane: {
2842-
SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
2843-
return BuildMI(BB, I, I.getDebugLoc(),
2844-
TII.get(SPIRV::OpGroupNonUniformElect))
2845-
.addDef(ResVReg)
2846-
.addUse(GR.getSPIRVTypeID(ResType))
2847-
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
2848-
}
2833+
case Intrinsic::spv_wave_any:
2834+
return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny);
2835+
case Intrinsic::spv_wave_is_first_lane:
2836+
return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformElect);
28492837
case Intrinsic::spv_wave_readlane:
2850-
return selectWaveReadLaneAt(ResVReg, ResType, I);
2838+
return selectWaveOpInst(ResVReg, ResType, I,
2839+
SPIRV::OpGroupNonUniformShuffle);
28512840
case Intrinsic::spv_step:
28522841
return selectExtInst(ResVReg, ResType, I, CL::step, GL::Step);
28532842
case Intrinsic::spv_radians:

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -630,6 +630,15 @@ void RequirementHandler::initAvailableCapabilities(const SPIRVSubtarget &ST) {
630630
addAvailableCaps({Capability::Shader, Capability::Linkage, Capability::Int8,
631631
Capability::Int16});
632632

633+
if (ST.isAtLeastSPIRVVer(VersionTuple(1, 3)))
634+
addAvailableCaps({Capability::GroupNonUniform,
635+
Capability::GroupNonUniformVote,
636+
Capability::GroupNonUniformArithmetic,
637+
Capability::GroupNonUniformBallot,
638+
Capability::GroupNonUniformClustered,
639+
Capability::GroupNonUniformShuffle,
640+
Capability::GroupNonUniformShuffleRelative});
641+
633642
if (ST.isAtLeastSPIRVVer(VersionTuple(1, 6)))
634643
addAvailableCaps({Capability::DotProduct, Capability::DotProductInputAll,
635644
Capability::DotProductInput4x8Bit,
@@ -676,14 +685,6 @@ void RequirementHandler::initAvailableCapabilitiesForOpenCL(
676685
if (ST.isAtLeastSPIRVVer(VersionTuple(1, 1)) &&
677686
ST.isAtLeastOpenCLVer(VersionTuple(2, 2)))
678687
addAvailableCaps({Capability::SubgroupDispatch, Capability::PipeStorage});
679-
if (ST.isAtLeastSPIRVVer(VersionTuple(1, 3)))
680-
addAvailableCaps({Capability::GroupNonUniform,
681-
Capability::GroupNonUniformVote,
682-
Capability::GroupNonUniformArithmetic,
683-
Capability::GroupNonUniformBallot,
684-
Capability::GroupNonUniformClustered,
685-
Capability::GroupNonUniformShuffle,
686-
Capability::GroupNonUniformShuffleRelative});
687688
if (ST.isAtLeastSPIRVVer(VersionTuple(1, 4)))
688689
addAvailableCaps({Capability::DenormPreserve, Capability::DenormFlushToZero,
689690
Capability::SignedZeroInfNanPreserve,

‎llvm/test/CodeGen/DirectX/WaveActiveAnyTrue.ll

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s | FileCheck %s
2+
3+
define noundef i1 @wave_any_simple(i1 noundef %p1) {
4+
entry:
5+
; CHECK: call i1 @dx.op.waveAnyTrue(i32 113, i1 %p1)
6+
%ret = call i1 @llvm.dx.wave.any(i1 %p1)
7+
ret i1 %ret
8+
}
9+
10+
declare i1 @llvm.dx.wave.any(i1)

‎llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveAnyTrue.ll

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
2+
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
3+
4+
; CHECK-DAG: %[[#bool:]] = OpTypeBool
5+
; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0
6+
; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 3
7+
; CHECK-DAG: OpCapability GroupNonUniformVote
8+
9+
; CHECK-LABEL: Begin function test_wave_any
10+
define i1 @test_wave_any(i1 %p1) #0 {
11+
entry:
12+
; CHECK: %[[#param:]] = OpFunctionParameter %[[#bool]]
13+
; CHECK: %{{.+}} = OpGroupNonUniformAny %[[#bool]] %[[#scope]] %[[#param]]
14+
%0 = call token @llvm.experimental.convergence.entry()
15+
%ret = call i1 @llvm.spv.wave.any(i1 %p1) [ "convergencectrl"(token %0) ]
16+
ret i1 %ret
17+
}
18+
19+
declare i1 @llvm.spv.wave.any(i1) #0
20+
21+
attributes #0 = { convergent }

0 commit comments

Comments
 (0)