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[fixup] Fix predicate condition, rename class, remove stray empty line
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3 files changed

+4
-5
lines changed

3 files changed

+4
-5
lines changed

llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -382,7 +382,7 @@ def NoUseScalarIncVL : Predicate<"!Subtarget->useScalarIncVL()">;
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def UseSVEFPLD1R : Predicate<"!Subtarget->noSVEFPLD1R()">;
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def UseUnaryUndefPseudos
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: Predicate<"!(Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME2()))">;
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: Predicate<"!(Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p2() || Subtarget->hasSME2p2()))">;
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def AArch64LocalRecover : SDNode<"ISD::LOCAL_RECOVER",
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SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -665,8 +665,8 @@ let Predicates = [HasSVEorSME] in {
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defm FNEG_ZPmZ : sve_int_un_pred_arit_bitwise_fp<0b101, "fneg", AArch64fneg_mt>;
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let Predicates = [HasSVEorSME, UseUnaryUndefPseudos] in {
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defm FABS_ZPmZ : sve_int_un_pred_arit_hsd<AArch64fabs_mt>;
669-
defm FNEG_ZPmZ : sve_int_un_pred_arit_hsd<AArch64fneg_mt>;
668+
defm FABS_ZPmZ : sve_fp_un_pred_arit_hsd<AArch64fabs_mt>;
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defm FNEG_ZPmZ : sve_fp_un_pred_arit_hsd<AArch64fneg_mt>;
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defm ABS_ZPmZ : sve_int_un_pred_arit_bhsd<AArch64abs_mt>;
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defm NEG_ZPmZ : sve_int_un_pred_arit_bhsd<AArch64neg_mt>;

llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -529,7 +529,6 @@ class SVE_1_Op_PassthruZero_Pat<ValueType vtd, SDPatternOperator op, ValueType v
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: Pat<(vtd (op (vtd (SVEDup0)), vt1:$Op1, vt2:$Op2)),
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(inst (IMPLICIT_DEF), $Op1, $Op2)>;
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532-
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class SVE_1_Op_Imm_OptLsl_Pat<ValueType vt, SDPatternOperator op, ZPRRegOp zprty,
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ValueType it, ComplexPattern cpx, Instruction inst>
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: Pat<(vt (op (vt zprty:$Op1), (vt (splat_vector (it (cpx i32:$imm, i32:$shift)))))),
@@ -4964,7 +4963,7 @@ multiclass sve_int_un_pred_arit_bitwise_fp_z<bits<3> opc, string asm, SDPatternO
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def : SVE_1_Op_PassthruUndefZero_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
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}
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4967-
multiclass sve_int_un_pred_arit_hsd<SDPatternOperator op> {
4966+
multiclass sve_fp_un_pred_arit_hsd<SDPatternOperator op> {
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def _H_UNDEF : PredOneOpPassthruPseudo<NAME # _H, ZPR16>;
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def _S_UNDEF : PredOneOpPassthruPseudo<NAME # _S, ZPR32>;
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def _D_UNDEF : PredOneOpPassthruPseudo<NAME # _D, ZPR64>;

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